CY7C68053Document # 001-06120 Rev *F Page 8 of 39
3.12.6 Default High-Speed Alternate Settings
3.13 External FIFO Interface
The architecture, control signals, and clock rates are
presented in this section.
3.13.1 Architecture
The FX2LP18 slave FIFO architecture has eight 512-byte
blocks in the endpoint RAM that directly serve as FIFO
memories and are controlled by FIFO control signals (such as
IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from
the SIE while the others are connected to the IO transfer logic.
The transfer logic takes two forms: the GPIF for internally
generated control signals or the slave FIFO interface for exter-
nally controlled transfers.
3.13.2 Master/Slave Control Signals
The FX2LP18 endpoint FIFO’s are implemented as eight
physically distinct 256x16 RAM blocks. The 8051/SIE can
switch any of the RAM blocks between two domains, the USB
(SIE) domain and the 8051-IO Unit domain. This switching is
instantaneous, giving zero transfer time between ‘USB FIFO’s’
and ‘Slave FIFO’s.’ Since they are physically the same
memory, no bytes are actually transferred between buffers.
At any given time, some RAM blocks are filling and emptying
with USB data under SIE control, while other RAM blocks are
available to the 8051 and/or the IO control unit. The RAM
blocks operate as single port in the USB domain, and dual port
in the 8051-IO domain. The blocks can be configured as
single, double, triple, or quad buffered as previously shown.
The IO control unit implements either an internal master (M for
master) or external master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls
FIFOADR[1:0] to select a FIFO. The two RDY pins can be
used as flag inputs from an external FIFO or other logic. The
GPIF can be run from either an internally derived clock or
externally supplied clock (IFCLK), at a rate that transfers data
up to 96 Megabytes/s (48 MHz IFCLK with 16-bit interface).
In Slave (S) mode, the FX2LP18 accepts either an internally
derived clock or externally supplied clock (IFCLK, maximum
frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE,
PKTEND signals from external logic. When using an external
IFCLK, the external clock must be present before switching to
the external clock with the IFCLKSRC bit. Each endpoint can
individually be selected for byte or word operation by an
internal configuration bit, and a Slave FIFO Output Enable
signal (SLOE) enables data of the selected width. External
logic must insure that the output enable signal is inactive when
writing data to a slave FIFO. The slave interface can also
operate asynchronously, where the SLRD and SLWR signals
act directly as strobes, rather than a clock qualifier as in
synchronous mode. The signals SLRD, SLWR, SLOE and
PKTEND are gated by the signal SLCS#.
3.13.3 GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the inter-
nally supplied interface clock: 30 MHz and 48 MHz. Alterna-
tively, an externally supplied clock of 5 MHz – 48 MHz feeding
the IFCLK pin can be used as the interface clock. IFCLK can
be configured to function as an output clock when the GPIF
and FIFO’s are internally clocked. An output enable bit in the
IFCONFIG register turns this clock output off. Another bit
within the IFCONFIG register will invert the IFCLK signal
whether internally or externally sourced.
3.14 GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user programmable finite state machine. It allows the
CY7C68053 to perform local bus mastering, and can
implement a wide variety of protocols such as ATA interface,
parallel printer port, and Utopia.
The GPIF has three programmable control outputs (CTL), and
two general purpose ready inputs (RDY). The data bus width
can be 8 or 16 bits. Each GPIF vector defines the state of the
control outputs, and determines what state a ready input (or
multiple inputs) must be before proceeding. The GPIF vector
can be programmed to advance a FIFO to the next data value,
advance an address, and so on. A sequence of the GPIF
vectors make up a single waveform that is executed to perform
the desired data move between the FX2LP18 and the external
device.
Notes
5. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Table 3-5. Default High-Speed Alternate Settings[3, 4]
Alternate Setting 0 1 2 3
ep0 64 64 64 64
ep1out 0 512 bulk[5] 64 int 64 int
ep1in 0 512 bulk[5] 64 int 64 int
ep2 0 512 bulk out (2×) 512 int out (2×) 512 iso out (2×)
ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×)
ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×)
ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×)
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