Cypress CY7C68053 manual Sequence Diagram of a Single and Burst Asynchronous Write

CY7C68053

9.13.4Sequence Diagram of a Single and Burst Asynchronous Write

Figure 9-18. Slave FIFO Asynchronous Write Sequence and Timing Diagram[17]

tSFA

tFAH

tSFA

tFAH

FIFOADR

t=0

tWRpwl

tWRpwh

T=0

tWRpwl

tWRpwh

tWRpwl

tWRpwh

tWRpwl

tWRpwh

SLWR

t =1

t=3

T=1

T=3

T=4

T=6

T=7

T=9

SLCS

tXFLG

tXFLG

FLAGS

tSFD

tFDH

tSFD

tFDH

tSFD

tFDH

tSFD

tFDH

DATA

N

N+1

N+2

N+3

t=2

T=2

T=5

T=8

tPEpwl

tPEpwh

PKTEND

Figure 9-18illustrates the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the 4-byte-short packet using PKTEND.

•At t = 0 the FIFO address is applied, ensuring that it meets the set-up time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications).

•At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum de-active pulse width of tWRpwh. If the SLCS is used, it must be asserted with SLWR or before SLWR is asserted.

•At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR.

•At t = 3, deasserting SLWR causes the data to be written from the data bus to the FIFO and then the FIFO pointer is

incremented. The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR.

The same sequence of events is shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note In the burst write mode, once SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incremented.

In Figure 9-18once the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed to the host using the PKTEND. The external device must be designed to not assert SLWR and the PKTEND signal at the same time. It must be designed to assert the PKTEND after SLWR is deasserted and meet the minimum deasserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion.

Document # 001-06120 Rev *F Page 36 of 39

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