Cypress CY7C68053 9.8 Slave FIFO Asynchronous Packet End Strobe

CY7C68053

Document # 001-06120 Rev *F Page 30 of 39

There is no specific timing requirement that needs to be met

for asserting the PKTEND pin with regards to asserting SLWR.

PKTEND can be asserted with the last data value clocked into

the FIFO’s or thereafter. The only consideration is that the set-

up time tSPE and the hold time tPEH must be met.

Although there are no specific timing requirements for the

PKTEND assertion, there is a specific corner case condition

that needs attention while using the PKTEND to commit a one

byte/word packet. There is an additional timing requirement

that needs to be met when the FIFO is configured to operate

in auto mode and you want to send two packets back to back:

a full packet (full defined as the number of bytes in the FIFO

meeting the level set in AUTOINLEN register) committed

automatically followed by a short one byte/word packet

committed manually using the PKTEND pin. In this particular

scenario, the user must make sure to assert PKTEND at least

one clock cycle after the rising edge that caused the last

byte/word to be clocked into the previous auto committed

packet. Figure 9-7 shows this scenario. X is the value the

AUTOINLEN register is set to when the IN endpoint is

configured to be in auto mode.

Figure9-7 shows a scenario whe re two packets are being

committed. The first packet gets committed automatically

when the number of bytes in the FIFO reaches X (value set in

AUTOINLEN register) and the second one byte/word short

packet is committed manually using PKTEND. Note that there

is at least one IFCLK cycle timing between the assertion of

PKTEND and clocking of the last byte of the previous packet

(causing the packet to be committed automatically). Failing to

adhere to this timing, results in the FX2LP18 failing to send the

one byte/word short packet.

9.8 Slave FIFO Asynchronous Packet End Strobe

Table 9-11. Slave FIFO Asynchronous Packet End Strobe Parameters[20]

Parameter Description Min. Max. Unit

tPEpwl PKTEND Pulse Width LOW 50 ns

tPWpwh PKTEND Pulse Width HIGH 50 ns

tXFLG PKTEND to FLAGS Output Propagation Delay 115 ns

IFCLK

SLWR

DATA

Figure 9-7. Slave FIFO Synchronous Write Sequence and Timing Diagram[17]

tIFCLK

>= tSWR >= tWRH

X-2

PKTEND

X-3

tFAH

tSPE tPEH

FIFOADR

tSFD tSFD tSFD

X-4

tFDH

tSFA

tSFD tSFD tSFD

X-1

tFDH

At least one IFCLK cycle

FLAGS

tXFLG

PKTEND tPEpwl

tPEpwh

Figure 9-8. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[17]

[+] Feedback