CY7C68053
Document # 001-06120 Rev *F Page 20 of 39
E6CF 1GPIFTCB2[10] GPIF Transaction Count
Byte 2
TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000RW
E6D0 1GPIFTCB1[10] GPIF Transaction Count
Byte 1
TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 00000000RW
E6D1 1GPIFTCB0[10] GPIF Transaction Count
Byte 0
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 00000001 RW
2Reserved 00000000RW
Reserved
Reserved
E6D2 1EP2GPIFFLGSEL[10]Endpoint 2 GPIF Flag
select
0 0 0 0 0 0 FS1 FS0 00000000RW
E6D3 1EP2GPIFPFSTOP Endpoint 2 GPIF stop
transaction on prog. flag
0 0 0 0 0 0 0 FIFO2FLAG 00000000RW
E6D4 1EP2GPIFTRIG[10] Endpoint 2 GPIF Trigger x x x x x x x x xxxxxxxx W
3Reserved
Reserved
Reserved
E6DA 1EP4GPIFFLGSEL[10]Endpoint 4 GPIF Flag
select
0 0 0 0 0 0 FS1 FS0 00000000RW
E6DB 1EP4GPIFPFSTOP Endpoint 4 GPIF stop
transaction on GPIF Flag
0 0 0 0 0 0 0 FIFO4FLAG 00000000RW
E6DC 1EP4GPIFTRIG[10] Endpoint 4 GPIF Trigger x x x x x x x x xxxxxxxx W
3Reserved
Reserved
Reserved
E6E2 1EP6GPIFFLGSEL[10]Endpoint 6 GPIF Flag
select
0 0 0 0 0 0 FS1 FS0 00000000RW
E6E3 1EP6GPIFPFSTOP Endpoint 6 GPIF stop
transaction on prog. flag
0 0 0 0 0 0 0 FIFO6FLAG 00000000RW
E6E4 1EP6GPIFTRIG[10] Endpoint 6 GPIF Trigger x x x x x x x x xxxxxxxx W
3Reserved
Reserved
Reserved
E6EA 1EP8GPIFFLGSEL[10]Endpoint 8 GPIF Flag
select
0 0 0 0 0 0 FS1 FS0 00000000RW
E6EB 1EP8GPIFPFSTOP Endpoint 8 GPIF stop
transaction on prog. flag
0 0 0 0 0 0 0 FIFO8FLAG 00000000RW
E6EC 1EP8GPIFTRIG[10] Endpoint 8 GPIF Trigger x x x x x x x x xxxxxxxx W
3Reserved
E6F0 1 XGPIFSGLDATH GPIF Data H
(16-bit mode only)
D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxxRW
E6F1 1XGPIFSGLDATLX Read/Write GPIF Data L &
trigger transaction
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E6F2 1XGPIFSGLDATL-
NOX
Read GPIF Data L, no
transaction trigger
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
E6F3 1GPIFREADYCFG Internal RDY, Sync/Async,
RDY pin states
INTRDY SAS TCXRDY5 0 0 0 0 0 00000000bbbrrrrr
E6F4 1GPIFREADYSTAT GPIF Ready Status 0 0 0 0 0 0 RDY1 RDY0 00xxxxxx R
E6F5 1GPIFABORT Abort GPIF Waveforms x x x x x x x x xxxxxxxx W
E6F6 2Reserved
ENDPOINT BUFFERS
E740 64 EP0BUF EP0-IN/-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E780 64 EP10UTBUF EP1-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E7C0 64 EP1INBUF EP1-IN buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E800 2048Reserved RW
F000 1024EP2FIFOBUF 512/1024-byte EP 2/slave
FIFO buffer (IN or OUT)
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
F400 512 EP4FIFOBUF 512 byte EP 4/slave FIFO
buffer (IN or OUT)
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
F600 512 Reserved
F800 1024EP6FIFOBUF 512/1024-byte EP 6/slave
FIFO buffer (IN or OUT)
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FC00 512 EP8FIFOBUF 512 byte EP 8/slave FIFO
buffer (IN or OUT)
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FE00 512 Reserved
xxxx I²C Configuration Byte 0DISCON 0 0 0 0 0 400KHZ xxxxxxxx
[13] n/a
Special Function Registers (SFRs)
80 1IOA[12] Port A (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
Table 5-1. FX2LP18 Register Summary (continued)
Hex SizeName Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access

Notes

12. SFRs not part of the standard 8051 architecture.

13. If no EEPROM is detected by the SIE then the default is 00000000.

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