Cypress CY7C68053 manual Sequence Diagram of a Single and Burst Asynchronous Read

CY7C68053

9.13.3Sequence Diagram of a Single and Burst Asynchronous Read

Figure 9-16. Slave FIFO Asynchronous Read Sequence and Timing Diagram[17]

t

SFA

t

t

SFA

tFAH

FAH

FIFOADR

t=0

tRDpwl

tRDpwh

tRDpwl

tRDpwh

tRDpwl

tRDpwh

tRDpwl tRDpwh

T=0

SLRD

t=2 t=3 T=2 T=3 T=4 T=5 T=6

SLCS

				tXFLG					tXFLG
FLAGS
		tXFD
						tXFD	tXFD	t
								XFD
DATA	Data (X)	N			N	N+1	N+2	N+3
	Driven
	t		t	OEoff	tOEon				tOEoff
	OEon

SLOE

t=1 t=4 T=1 T=7

Figure 9-17. Slave FIFO Asynchronous Read Sequence of Events Diagram

FIFO POINTER

SLOE

SLRD

SLRD

SLOE

SLOE

SLRD

SLRD

SLRD

SLRD

SLOE

N

N

N

N+1

N+1

N+1

N+1

N+2

N+2

N+3

N+3

FIFO DATA BUS

Not Driven Driven: X N

N Not Driven N N+1 N+1 N+2 N+2 Not Driven

Figure 9-16illustrates the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read.

•At t = 0, the FIFO address is stable and the SLCS signal is asserted.

•At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is previous data; it is data that was in the FIFO from a prior read cycle.

•At t = 2, SLRD is asserted. The SLRD must meet the min- imum active pulse of tRDpwl and minimum de-active pulse width of tRDpwh. If SLCS is used then, SLCS must be as- serted with SLRD or before SLRD is asserted (for example, the SLCS and SLRD signals must both be asserted to start a valid read condition).

•The data that is driven, after asserting SLRD, is the updated data from the FIFO. This data is valid after a propagation delay of tXFD from the activating edge of SLRD. In Figure 9- 16, data N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle (for example, SLRD is asserted), SLOE MUST be in an asserted state. SLRD and SLOE can also be tied together.

The same sequence of events is also shown for a burst read marked with T = 0 through 5. Note In burst read mode, during SLOE assertion, the data bus is in a driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented.

Document # 001-06120 Rev *F Page 35 of 39

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