CY7C68053
Document # 001-06120 Rev *F Page 15 of 39
2G IFCLK I/O/Z Z Interface Clock, used for synchronously clocking data into or out of the
slave FIFO’s. IFCLK also serves as a timing reference for all slave FIFO
control signals and GPIF. When internal clocking is used (IFCONFIG.7= 1)
the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5
and IFCONFIG.6. IFCLK may be inverted, whether internally or externally
sourced, by setting the bit IFCONFIG.4 =1.
7B WAKEUP Input N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the
oscillator and interrupts the 8051 to allow it to exit the suspend mode.
Holding WAKEUP asserted inhibits the MoBL-USB chip from
suspending. This pin has programmable polarity (WAKEUP.4).
3F SCL OD Z Clock for the I2C interface. Connect to VCC_IO or VCC with a 2.2K - 10K
pull up resistor. (An I2C peripheral is required).
3G SDA OD Z Data for the I2C interface. Connect to VCC_IO or VCC with a 2.2K - 10K pull
up resistor. (An I2C peripheral is required).
5A VCC_IO Power N/A VCC. Connect this pin to 1.8V to 3.3V power source.
Appropriate bulk/bypass capacitance should be provided for this
supply rail.
5B VCC_IO Power N/A VCC. Connect this pin to 1.8V to 3.3V power source
7E VCC_IO Power N/A VCC. Connect this pin to 1.8V to 3.3V power source.
8E VCC_IO Power N/A VCC. Connect this pin to 1.8V to 3.3V power source.
5C VCC_D Power N/A VCC. Connect this pin to 1.8V power source.(Supplies power to internal
digital 1.8V circuits)
Appropriate bulk/bypass capacitance should be provided for this
supply rail.
1G VCC_A Power N/A VCC. Connect this pin to 1.8V power source.(Supplies power to internal
analog 1.8V circuits)
1H GND Ground N/A Ground.
2H GND Ground N/A Ground.
4A GND Ground N/A Ground.
4B GND Ground N/A Ground.
4C GND Ground N/A Ground.
7D GND Ground N/A Ground.
8D GND Ground N/A Ground.
Table 4-1. FX2LP18 Pin Descriptions (continued)[9]
56 VFBGA Name Type Default Description
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