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CY7C68053
Figure 4-2. CY7C68053 56-pin VFBGA Pin Assignment - Top view
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39 pages, 1.21 Mb
CY7C68053
Document # 001-06120 Rev *F
Page 11 of 39
Figure 4-2. CY7C68053 56-pin VF
BGA Pin Assignment - Top view
12345678
A
B
C
D
E
F
G
H
1A 2A 3A 4A 5A 6A 7A 8A
1B 2B 3B 4B 5B 6B 7B 8B
1C 2C 3C 4C 5C 6C 7C 8C
1D 2D
7D 8D
1E 2E
7E 8E
1F 2F 3F 4F 5F 6F 7F 8F
1G 2G 3G 4G 5G 6G 7G 8G
1H 2H 3H 4H 5H 6H 7H 8H
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Contents
Main
MoBL-USB FX2LP18 USB Microcontroller
1.0 CY7C68053 Features
MoBL-USB FX2LP18
Block Diagram
2.0 Applications
3.0 Functional Overview
3.1 USB Signaling Speed
3.2 8051 Microprocessor
CY7C68053
3.3 I2C Bus
3.4 Buses
3.5 USB Boot Methods
3.6 ReNumeration
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CY7C68053
3.9 Reset and Wakeup
CY7C68053
3.10 Program/Data RAM
3.11 Register Addresses
3.12 Endpoint RAM
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CY7C68053
3.13 External FIFO Interface
3.14 GPIF
3.15 ECC Generation
3.16 USB Uploads and Downloads
3.17 Autopointer Access
3.18 I2C Controller
4.0 Pin Assignments
Port GPIF Master Slave FIFO
Figure 4-2. CY7C68053 56-pin VFBGA Pin Assignment - Top view
4.1 CY7C68053 Pin Descriptions
Appropriate bulk/bypass capacitance should be provided for this
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5.0 Register Summary
Note 11. The register can only be reset, it cannot be set.
Table 5-1. FX2LP18 Register Summary (continued)
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Document # 001-06120 Rev *F Page 20 of 39
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6.0 Absolute Maximum Ratings
7.0 Operating Conditions
8.0 DC Characteristics
9.0 AC Electrical Characteristics
9.1 USB Transceiver
9.2 GPIF Synchronous Signals
9.3 Slave FIFO Synchronous Read
9.4 Slave FIFO Asynchronous Read
9.5 Slave FIFO Synchronous Write
9.6 Slave FIFO Asynchronous Write
9.7 Slave FIFO Synchronous Packet End Strobe
9.8 Slave FIFO Asynchronous Packet End Strobe
9.9 Slave FIFO Output Enable
9.10 Slave FIFO Address to Flags/Data
9.11 Slave FIFO Synchronous Address
9.12 Slave FIFO Asynchronous Address
9.13 Sequence Diagram
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10.0 Ordering Information
11.0 Package Diagram
Table 10-1. Ordering Information Ordering Code Package Type RAM Size # Prog I/Os
12.0 PCB Layout Recommendations
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