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Cypress CY7C68053 manual Pin Assignments, 18.2 I2C Interface Boot Load Access

Models: CY7C68053

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CY7C68053

Table 3-6. Strap Boot EEPROM Address Lines to These Values

Bytes	Example EEPROM	A2	A1	A0
16	24AA00[8]	N/A	N/A	N/A
128	24AA01	0	0	0

256	24AA02	0	0	0

4K	24AA32	0	0	1

8K	24AA64	0	0	1

16K	24AA128	0	0	1

3.18.2I2C Interface Boot Load Access

At power on reset the I2C interface boot loader loads the VID/PID/DID and configuration bytes and up to 16 kBytes of program/data. The available RAM spaces are 16 kBytes from

0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051 is reset. I2C interface boot loads only occur after power on reset.

3.18.3I2C Interface General Purpose Access

The 8051 can control peripherals connected to the I2C bus using the I2CTL and I2DAT registers. FX2LP18 provides I2C master control only, it is never an I2C slave.

4.0Pin Assignments

Figure 4-1identifies all signals for the package. It is followed by the pin diagram.Three modes are available: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power on default configuration.

Figure 4-1. Signals

Port

GPIF Master

Slave FIFO

XTALIN XTALOUT RESET# WAKEUP#

SCL

SDA

IFCLK CLKOUT

DPLUS DMINUS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

PA5

PA6

PA7

FD[15]

FD[14]

FD[13]

FD[12]

FD[11] FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

RDY0 RDY1

CTL0 CTL1 CTL2

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

PA5

PA6

PA7

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

SLRD

SLWR

FLAGA

FLAGB

FLAGC

INT0#/PA0

INT1#/PA1

SLOE WU2/PA3

FIFOADR0

FIFOADR1

PKTEND PA7/FLAGD/SLCS#

Note

8.This EEPROM does not have address pins.

Document # 001-06120 Rev *F

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Cypress CY7C68053 manual Pin Assignments, 18.2 I2C Interface Boot Load Access, 18.3 I2C Interface General Purpose Access

Contents

Block Diagram CY7C68053 FeaturesCypress Semiconductor Corporation Functional Overview USB Signaling SpeedApplications 8051 MicroprocessorI2C Bus USB Boot MethodsBus-powered Applications BusesINT2 USB Interrupts Priority INT2VEC Value SourceReset Timing Values Reset and WakeupCondition Register Addresses Program/Data RAMEndpoint RAM Default Full-Speed Alternate Settings Default Full-Speed Alternate Settings3External Fifo Interface Default High-Speed Alternate Settings3Gpif ECC Generation6 Autopointer AccessUSB Uploads and Downloads 18 I2C Controller18.3 I2C Interface General Purpose Access 18.2 I2C Interface Boot Load AccessPin Assignments CY7C68053 56-pin Vfbga Pin Assignment Top view FX2LP18 Pin Descriptions Name Type Default DescriptionCY7C68053 Pin Descriptions Port aPktend FIFOADR0FIFOADR1 SLCS#Flaga IFCONFIG10 Slrd IFCONFIG10Slwr IFCONFIG10 Flagb IFCONFIG10Ground Register Summary FX2LP18 Register SummaryECC2B0 ECC1B2COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 ECC2B1EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN Qenable Qstate QSIGNAL2 QSIGNAL1 QSIGNAL0Epie Gpifwf GpifdoneEP1INCS EP1OUTCSBusy Stall EP2CSTC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 E6CFTC9 TC8 EP2GPIFFLGSELDPH0 AutoptrsetupDPL0 SELTL2 RCAP2LRCAP2H TH2Absolute Maximum Ratings Operating ConditionsDC Characteristics Gpif Synchronous Signals AC Electrical CharacteristicsUSB Transceiver Slave Fifo Synchronous Read Timing Diagram17 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram17 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram17 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressIfclk Sequence DiagramSingle and Burst Synchronous Read Example Sloe SlrdSingle and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read 17. Slave Fifo Asynchronous Read Sequence of Events DiagramSequence Diagram of a Single and Burst Asynchronous Write Ordering Information Package DiagramDevelopment Tool Kit PCB Layout Recommendations OSG Issue Date Orig. Description of ChangeDocument History ARI