
Processor 1 | channel 1: memory sockets A1 and A4 |
| channel 2: memory sockets A2 and A5 |
| channel 3: memory sockets A3 and A6 |
Processor 2 | channel 1: memory sockets B1 and B4 |
| channel 2: memory sockets B2 and B5 |
| channel 3: memory sockets B3 and B6 |
General Memory Module Installation Guidelines
This system supports Flexible Memory Configuration, enabling the system to be configured and run in any valid chipset architectural configuration. The following are the recommended guidelines for best performance:
•UDIMMs and RDIMMs must not be mixed.
•x4 and x8 DRAM based DIMMs can be mixed. For more information, see
•A maximum of two UDIMMs can be populated in a channel.
•A maximum of two
•A maximum of two single- or
•One
•Populate DIMM sockets only if a processor is installed. For
•Populate all sockets with white release tabs first and then black.
•Populate the sockets by highest rank count in the following order - first in sockets with white release levers and then black. For example, if you want to mix
•In a
•Memory modules of different sizes can be mixed provided that other memory population rules are followed (for example, 2 GB and 4 GB memory modules can be mixed).
•Depending on
•If memory modules with different speeds are installed, they will operate at the speed of the slowest installed memory module(s) or slower depending on system DIMM configuration.
Mode-Specific Guidelines
Three memory channels are allocated to each processor. The allowable configurations depend on the memory mode selected.
NOTE: x4 and x8 DRAM based DIMMs can be mixed providing support for (Reliability, Availability, and Serviceability) RAS features. However, all guidelines for specific RAS features must be followed. x4 DRAM based DIMMs retain Single Device Data Correction (SDDC) in either memory optimized (independent channel) or Advanced ECC modes. x8 DRAM based DIMMs require Advanced ECC mode to gain SDDC.
The following sections provide additional slot population guidelines for each mode.
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