Freescale Semiconductor MCF52210, MCF52211, MCF52212, MCF52213 10.6.1.1 Power-On Reset, 10.6.1.2 External Reset, 10.6.1.3 Loss-of-Clock Reset, 10.6.1.4 Loss-of-Lock Reset, 10.6.1.5 Software Reset, 10.6.1.6 LVD Reset

Reset Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
10-6 Freescale Semiconductor
Internal byte, word, or longword writes are guaranteed to complete without data corruption when a
synchronous reset occurs. External writes, including longword writes to 16-bit ports, are also guaranteed
to complete.
Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does
not wait for the current bus cycle to complete. Reset is asserted immediately to the system.
10.6.1.1 Power-On Reset
At power up, the reset controller asserts RSTO. RSTO continues to be asserted until VDD has reached a
minimum acceptable level and, if PLL clock mode is selected, until the PLL achieves phase lock. Then
after approximately another 512 cycles, RSTO is negated and the part begins operation.
10.6.1.2 External Reset
Asserting the external RSTI for at least four rising CLKOUT edges causes the exte rnal reset request to be
recognized and latched. The bus monitor is enabled and the current bus cycle is completed. The reset
controller asserts RSTO for approximately 512 cycles after RSTI is negated and the PLL has acquired lock.
The part then exits reset and begins operation.
In low-power stop mode, the system clocks are stopped. Asserting the external RSTI in stop mode causes
an external reset to be recognized.
10.6.1.3 Loss-of-Clock Reset
This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set and the PLL
reference or the PLL itself fails. Th e reset controller asserts RST O for approximately 512 cycles after the
PLL has acquired lock. The device then exits reset and begins operation.
10.6.1.4 Loss-of-Lock Reset
This reset condition occurs in PLL clock mode when the LOLRE bit in the SYNCR is set and the PLL
loses lock. The reset controller asserts RSTO for approximately 512 cycles after the PLL has acquired
lock. The device then exits reset and resumes operation.
10.6.1.5 Software Reset
A software reset occurs when the SOFTRST bit is set. If the RSTI is negated and the PLL has acquired
lock, the reset controller asserts RSTO for approximately 512 cycles. Then the device exits reset and
resumes operation.
10.6.1.6 LVD Reset
The LVD reset occurs when the supply input voltage, VDD, drops below VLVD (minimum).