Overview
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 1-5
Up to 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access
with standby power supply support
Up to 128 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management
Fully static operation with processor sleep and whole chip stop modes
Rapid response to interrupts from the low-power sleep mode (wake-up feature)
Clock enable/disable for each peripheral when not used (except backup watchdog timer)
Software controlled disable of external clock output for low-power consumption
Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller
Full-speed / low-speed host controller
USB 1.1 and 2.0 compliant full-speed / low speed device controller
16 bidirectional end points
DMA or FIFO data stream interfaces
Low power consumption
OTG protocol logic
Three universal asynchronous/synchronous receiver transmitters (UARTs)
16-bit divider for clock generation
Interrupt control logic with maskable interrupts
DMA support
Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
Up to two stop bits in 1/16 increments
Error-detection capabilities
Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
Transmit and receive FIFO buffers
•Two I
2C modules
Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
Fully compatible with industry-standard I2C bus
Master and slave modes support multiple masters
Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI)
Full-duplex, three-wire synchronous transfers
Up to four chip selects available
Master mode operation only
Programmable bit rates up to half the CPU clock frequency
Up to 16 pre-programmed transfers
Fast analog-to-digital converter (ADC)
Eight analog input channels