Analog-to-Digital Converter (ADC)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 26-29
bit is 1, when the SYNC0 input goes high. A scan ends when the first disabled sample slot is encountered
in the SDIS register. Completion of the scan triggers the EOSI0 interrupt if the interrupt is enabled by the
EOSIE0 bit. The START0 bit and SYNC0 input are ignored while a scan is in process. Scanning stops and
cannot be initiated when the STOP0 bit is set.
Parallel scans differ in that convert er A collects up to 4 samples (SAMPLE 0-3) in parallel to converter B
collecting up to 4 samples (SAMPLE 4-7). SAMPLEs 0-3 may only reference inputs AN0-3, and
SAMPLEs 4-7 may only reference inputs AN4-7. W ithin these constraints, any sample may reference any
pin and the same input may be referenced by more than one sample slot.
By default (when SIMULT=1), parallel scans of the converters are initiated together when the STAR T0 bit
is written as 1 or, if the SYNC0 bit is 1, when the SYNC0 input goes high. The scan in both converters
terminates when either converter encounters a disabled sample slot in SDIS. Completion of a scan triggers
the EOSI0 interrupt provided the EOSIE0 interrupt enable is set. Samples are always taken simultaneously
in the A and B converters. Setting the STOP0 bit stops and prevents the initiation of scanning in both
converters.
Setting SIMULT equal to 0 (non-simultaneous mode) causes parallel scanning to operate independently in
the A and B converter. Each converter has its own set of STARTn, STOPn, SYNCn, and EOSIEn control
bits, SYNCn input, EOSIn interrupt, and CIPn status indicators (n = 0 for converter A, n = 1 for converter
B). Although continuing to operate in parallel, the scans in the A and B converter start and stop
independently according to their own controls. They may be simultaneous, phase shifted, or asynchronous,
depending on when scans are initiated on the respective converters. The A and B converter may be of
different length (up to a maximum of four) and each converter’s scan completes when a disabled sample
is encountered in that converters sample list only. STOP0 only stops the A converter, and STOP1 only
stops the B converter . Looping scan modes repeat independently , with the A converter capturing SAMPLE
0-3, and B converter capturing SAMPLE 4-7. In loop modes, each converter independently restarts its scan
after capturing its samples.

26.5.5 Scan Sequencing

Scan modes break down into three types based on how they repeat: once, triggered, or loop. Be certain to
read Section 26.5.4, “Sequential vs. Parallel Sampling” to understand the operation of sequential and
parallel scan modes before proceeding.
During a once mode scan, a single sequential or parallel scan is executed. Once scan modes differ from
triggered scan modes in that they must be re-armed after each use. While all scan modes ignore sync pulses
occurring while a scan is in process, once scan modes continues to ignore sync pulses even after the scan
completes until re-armed. However, re-arming can occur any time, including during the scan, by writing
to a CTRLn register. If operating in a sequential mode or simultaneous parallel, write to the CTRL1
register. If operating in a non-simultaneous parallel mode, re-arm converter A by writing to the CTRL1
register and converter B by writing to the CTRL2 register.
Triggered scan modes are identical to the corresponding once scan modes, except that re-arming of sync
inputs is not necessary.
Loop scan modes automatically restart a scan as soon as the previous scan completes. In the loop
sequential mode, up to 8 samples are captured in each loop, and the next scan starts immediately after the