Analog-to-Digital Converter (ADC)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 26-33
PUDELAY ADC clock cycles execute at the start of all scans while the ADC engages the conversion clock
and the ADC powers up, stabilizing in the standby current mode. This provides the lowest possible power
configuration for ADC operation.
3. Auto standby mode
This mode operates when:
— At least one ADC converter is powered up (PD0 or PD1=0 in the POWER register);
— Auto power-down is disabled (APD=0 in the POWER register);
— Auto standby is enabled (ASB=1 in the POWER register);
— The ADC’s clock is enabled (ADC=1 in the SIM module’s SIM_PCE register);
— The relaxation oscillator must be enabled for 8-MHz operation or the external oscillator clock
must be running at 8 MHz in this mode.
In auto standby mode, the ADC uses the conversion clock when active and the100 kHz Standby clock
when idle. The standby (low current) state automatically engages when the ADC is idle. The ADC
executes a startup delay of PUDELAY ADC clocks at the start of all scans, allowing the ADC to switch to
the Conversion clock and to revert from standby to normal current mode.
It is recommended the conversion clock be configured at or near 5.0 MHz to minimize conversion latency
when active. In this mode, the ADC uses the conversion clock when active and gates off the conversion
clock and powers down the converters when idle. A startup delay of PUDELAY ADC clocks is executed
at the start of all scans, allowing the ADC to stabilize when switching to normal current mode from a
completely powered off condition. This mode uses less power than normal and more power than auto
standby . It requires more startup latency than auto standby when leaving the idle state to start a scan (higher
PUDELAY value).
4. POWER-DOWN MODE
This mode operates when:
— Both ADC converters are powered down (PD0=PD1=1 in the POWER register);
— The ADC’s clock is disabled (ADC=0 in the SIM module’s SIM_PCE register).
In this configuration, the clock trees to the ADC and all of its analog components are shut down
and the ADC uses no power.

26.5.8.2 Power Management Details

The ADC voltage reference and converters are powered down (PDn=1 in the POWER register) on reset.
Individual converters can be manually powered down when not in use (PD0=1 or PD1=1), and the voltage
reference can be automatically powered down when no converter is in use (PD2=1) or manually powered
up when no converters are powered (PD2=0). When the ADC voltage reference is powered down, output
reference voltages are set to low (VSSA).
A delay of PUDELAY ADC clock cycles is imposed when PD0 or PD1 are cleared to power-up a converter
and when the ADC goes from an idle (neither converter has a scan in process) to an active state when not
operating in normal power mode. The ADC is active when at least one converter has a scan in process. A
device recommends the use of two PUDELAY values: a large value for full power -up and a smaller value
for going from standby current levels to full power-up. The following paragraphs provide an explanation
of how to use PUDELAY when starting the ADC up or changing modes.