General Purpose I/O Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
13-6 Freescale Semiconductor

Setting any bit in a DDRn register configures the corresponding port n pin as an output. Clearing any bit

in a DDRn register configures the corresponding pin as an input.

IPSBAR
Offsets:
0x10_002C (DDRDD)
0x10_0022 (DDRAN)
Access: User read/write
76543210
RDDRn7DDRn6DDRn5DDRn4 DDRn3 DDRn2 DDRn1 DDRn0
W
Reset:00000000

Figure 13-7. Port Data Direction Registers with Bits 7:0 Implemented (DDRDD, DDRAN)

IPSBAR
Offsets:
0x10_0026 (DDRTA)
0x10_0027 (DDRTC)
0x10_0028 (DDRTD)
0x10_0029 (DDRUA)
0x10_002A (DDRUB)
0x10_002B (DDRUC)
Access: User read/write
76543210
R0 0 0 0 DDRn3 DDRn2 DDRn1 DDRn0
W
Reset:00000000

Figure 13-8. Port Data Direction Registers with Bits 3:0 Implemented (DDRTA, DDRTC, DDRTD, DDRUA,

DDRUB, DDRUC)

IPSBAR
Offset: 0x10_0024 (DDRQS)
Access: User read/write
76543210
R0DDRn6DDRn5DDRn4 DDRn3 DDRn2 DDRn1 DDRn0
W
Reset:00000000

Figure 13-9. Port QS Data Direction Register (DDRQS)

IPSBAR
Offset: 0x10_0020 (DDRNQ)
Access: User read/write
76543210
RDDRn7DDRn6DDRn5DDRn4 DDRn3 DDRn2 DDRn10
W
Reset:00000000

Figure 13-10. Port NQ Data Direction Register (DDRNQ)