IEEE 1149.1 Test Access Port (JTAG)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
29-10 Freescale Semiconductor
to a single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary
scan register.

29.4.3.9 BYPASS Instruction

The BYPASS instruction selects the bypass register, creating a single-bit shift register path from the TDI
pin to the TDO pin. BYPASS enhances test efficiency by reducing the overall shift path when a device
other than the ColdFire processor is the device under test on a board design with multiple chips on the
overall boundary scan chain. The shift register lsb is forced to logic 0 on the rising edge of TCLK after
entry into the capture-DR state. Therefore, the first bit shifted out after selecting the bypass register is
always logic 0. This differentiates parts that support an IDCODE regi ster from parts that support only the
bypass register.

29.5 Initialization/Application Information

29.5.1 Restrictions

The test logic is a static logic design, and TCLK can be stopped in a high or low state without loss of data.
However, the system clock is not synchronized to TCLK internally. Any mixed operation using the test
logic and system functional logic requires external synchronization.
Using the EXTEST instruction requires a circuit-board test environment that avoids device-destructive
configurations in which MCU output drivers are enabled into actively driven networks.
Low-power stop mode considerations:
The TAP controller must be in the test-logic-reset state to enter or remain in the low-power stop
mode. Leaving the test-logic-reset state negates the ability to achieve low-power, but does not
otherwise affect device functionality.
The TCLK input is not blocked in low-power stop mode. To consume minimal power, the TCLK
input should be externally connected to VDD.
The TMS, TDI, and TRST pins include on-chip pull-up resistors. For minimal power consumption
in low-power stop mode, these three pins should be connected to VDD or left unconnected.

29.5.2 Nonscan Chain Operation

Keeping the TAP controller in the test-logic-reset state ensures that the scan chain test logic is transparent
to the system logic. It is recommended that TMS, TDI, TCLK, and TRST be pulled up. TRST could be
connected to ground. However, because there is a pull-up on TRST, some amount of current results. The
internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without
asserting TRST.