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CHAPTER 3 CLOCK GENERATOR AND CONTROLLER
3.10 Standby Mode (Low Power Consumption Mechanism)

The standby mode implies the stop state and sleep state.

Outline of Stop State
In the stop state, all internal clocks and the operation of th e oscilla tion circui t are sto pped so a s
to minimize power consumption.
Proceed as follows to shift to the stop state:
Using an instruction to write to the standby control register (STCR)
Perform one of the following to return to the operating state:
Interrupt r equest (limited to the pe ripherals that permit an interrupt request to occur even in
the stop state)
Applying the L level to the RSTX pin
Since all internal clocks are stopped in the stop stat e, internal peripherals oth er than those t hat
cause an interrupt to return remain stopped.
Outline of Sleep State
In the sleep state, the CPU clock and internal bus clock are stopped. Power consumption when
CPU operation is not required can be suppressed to a certain degr ee.
Proceed as follows to transit to the sleep state:
Using an instruction to write to the standby control register (STCR)
Perform one of the following to to return to the operating state :
Interrupt r equest
Issue a reset cause
Since the internal DMA clock and peripheral clock o perate in the sleep state, the sleep state can
be canceled by causing an interrupt from any of the int ernal periphe rals th at use one of the two
clock sources.
Types of Operation in Standby Mode
Table 3.10.1 lists the types of operations performed in standby mode.
Y: Operating X: Stopped
Table 3.10-1 Types of Operation in Standby Mode
Operating
status Transition
condition Oscillator Internal clock Peripheral Pin Cancel
method
CPU/
internal bus DMA/
peripheral
Run Y Y Y Y Active
Sleep STCR
SLEP = 1 YX YYActive
Stop STCR
STOP = 1 XX XX*