Fujitsu FR30 4.17.6 Automatic Wait Cycles

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4.17 Bus Timing
4.17.6 Automatic Wait Cycles
This section provides an automatic wait cycle timing chart.
■Automatic Wait Cycle Timing Chart
❍Bus width: 16 bits, access: half-word read/write
Figure 4.17-14 Example of Automatic Wait Cycle Timing Chart
[Explanation of operation]
• When im pl eme nti ng auto mat ic wai t cy cles , s et the W TC bi t o f th e AMD register for each chip
select area.
• The ab ove exa mple is a n exampl e the WTC bi ts a re set "001" to i nsert o ne wai t bus cycl e in
the usual bus cycles. In this case, it follows that "2 usual clock bus cycles" + "1 wait clock
cycle" = "3 clock bus cycles".
Up to 7 clock cycles of automatic wait (usual bus cy cles: 9 clock cycles) can be specified.
BA1 BA1 BA2 BA1 BA1 BA2
CLK
A24-00 #0 #2
D31-16 #0:1 #2,3
RDX
WR0X,1X
(DACK0)
(EOP0)
Wait Wait
Read Write