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CHAPTER 3 CLOCK GENERATOR AND CONTROLLER
Figure 3.11-2 Watchdog Timer Operating Timing
<Note>
The tim e interval between the first A5H and the next 5AH is not specified. Watchdog
resetting is postponed only if the time interv al from one 5AH to the next 5AH is within the time
specified by the WT bits and one A5H is written b etween them.
If the first A5H is fol lowed by something oth er than 5AH, the first A5H is ignored . Therefore,
A5H must be written again.
Timebase Timer
The timebase timer is used to supply clock pulses to the watchdo g ti mer an d is used also as the
oscillation stabilization wait timer. The operating clock φ is double the X0 when the GCR CHC is
1 or the cycle of the PLL oscillation frequency when the GCR CH C is 0.
The value of this timebase timer is set in the RFCR and used as the count clock for the count
value for DRAM refresh.
Figure 3.11-3 Timebase Timer Counter
Watchdog start
Watchdog clear
Watchdog resetting
Timebase timer overflow
Watchdog flip-flop
WTE write
1/2
1
1/2
2
1/2
3
1/218 1/219 1/220 1/221