xiii
Figure 3.15-1 Example of PLL Clock Setting ................................................................................................. 108
Figure 3.15-2 Clock System Reference Diagram ........................................ .................................................. 109
Figure 4.1-1 Bus Interface Registers ...... ...... ....... ...... ....... ........................................................................... 113
Figure 4.1-2 Bus Interface Block Diagram .............................. ..................................................................... 114
Figure 4.2-1 Example of Setting Chip Select Areas ................................... .................................................. 115
Figure 4.4-1 Sample Maps of the Chip Select Areas . .................................................................................. 120
Figure 4.16-1 Data bus Widths and Control Signals in Usual Bus Interface .................................................. 139
Figure 4.16-2 Data Bus Widths and Control Signals in DRAM Interface ....................................................... 1 39
Figure 4.16-3 Relationship between Internal Register and External Data Bus for Word Ac cess .................. 141
Figure 4.16-4 Relationship between Internal Register and External Data Bus for Half-Word A ccess ........... 141
Figure 4.16-5 Relationship between Internal Register and External Data Bus for Byte A ccess .................... 142
Figure 4.16-6 Relationship between Internal Register and External Data Bus for 16-bit Bu s Width .. ........... 142
Figure 4.16-7 Relationship between Internal Register and External Data Bus for 8-bit Bus Width .... ........... 143
Figure 4.16-8 External Bus Access for 16-bit Bus Width ............................................................................... 144
Figure 4.16-9 External Bus Access for 8-bit Bus Width ................................................................................. 145
Figure 4.16-10 Example of Connection between MB91F109 and External Devices ....................................... 146
Figure 4.16-11 Relationship between Internal Register and External Data Bus for Word Access . ................. 147
Figure 4.16-12 Relationship between Internal Register and External Data Bus for Half-word Access ........ .... 148
Figure 4.16-13 Relationship between Internal Register and External Data Bus for Byte Access .................... 148
Figure 4.16-14 Relationship between Internal Register and External Data Bus for 16-bit Bus Width ............. 149
Figure 4.16-15 Relationship between Internal Register and External Data Bus for 8-bit Bus Width ............... 149
Figure 4.16-16 Example of Connection between MB91F109 and External Devices (16-Bit B us Width) ......... 150
Figure 4.16-17 Example of Connection between MB91F109 and External Devices (8-Bit Bu s Width) ........... 150
Figure 4.16-18 Example of Connection between MB91F109 and One 8-bit Output DRAM (8-Bit Data Bus) . 156
Figure 4.16-19 Example of Connection between MB91F109 and Two 8-Bit Output DRAMs
(16-Bit Data Bus) ............................. ........................................................................................ 157
Figure 4.16-20 Example of Connection between MB91F109 and Two 16-Bit Output DRAMs
(16-Bit Data Bus) ............................. ........................................................................................ 158
Figure 4.17-1 Example of Basic Read Cycle Timing Chart .................... ........................................................ 162
Figure 4.17-2 Example for Basic Write Cycle Timing ............................ ........................................................ 164
Figure 4.17-3 Example 1 of Read Cycle Timing Chart ................................ .................................................. 166
Figure 4.17-4 Example 2 of Read Cycle Timing Chart ................................ .................................................. 166
Figure 4.17-5 Example 3 of Read Cycle Timing Chart ................................ .................................................. 166
Figure 4.17-6 Example 4 of Read Cycle Timing Chart ................................ .................................................. 167
Figure 4.17-7 Example 5 of Read Cycle Timing Chart ................................ .................................................. 167
Figure 4.17-8 Example 1 of Write Cycle Timing Chart ........................... ........................................................ 168
Figure 4.17-9 Example 2 of Write Cycle Timing Chart ........................... ........................................................ 168
Figure 4.17-10 Example 3 of Write Cycle Timing Chart ........................................................... ........................ 168
Figure 4.17-11 Example 4 of Write Cycle Timing Chart ........................................................... ........................ 169