viii
3.9 Gear Function .................................................................................................. ................................... 87
3.10 Standby Mode (Low Power Consumption Mechanism) ...................................................................... 90
3.10.1 Stop State ...................................................... ................................................................................ 92
3.10.2 Sleep State ................... ............................................................................................................. .... 95
3.10.3 Standby Mode State Transition .................................................................. ................................... 98
3.11 Watchdog Function ...... .............................................................................................................. ......... 99
3.12 Reset Source Hold Circuit ............................................................ ..................................................... 101
3.13 DMA Suppression .............. ........................................................................................................ ....... 103
3.14 Clock Doubler Function ................................................................ ..................................................... 105
3.15 Example of PLL Clock Setting ......................................... ................................................................. 108
CHAPTER 4 BUS INTERFACE ..................................................................................... 111
4.1 Outline of Bus Interface ......................................................... ........................................................... 112
4.2 Chip Select Area .......... .............................................................................................................. ....... 115
4.3 Bus Interface ................................................ ..................................................................................... 116
4.4 Area Select Register (ASR) and Area Mask Register (AMR) ................... ........................................ 118
4.5 Area Mode Register 0 (AMD0) ............................................................ .............................................. 121
4.6 Area Mode Register 1 (AMD1) ............................................................ .............................................. 123
4.7 Area Mode Register 32 (AMD32) ........................................................ .............................................. 124
4.8 Area Mode Register 4 (AMD4) ............................................................ .............................................. 125
4.9 Area Mode Register 5 (AMD5) ............................................................ .............................................. 126
4.10 DRAM Control Register 4/5 (DMCR4/5) ............................................................................. .............. 127
4.11 Refresh Control Register (RFCR) ... ........................................................................................... ....... 130
4.12 External Pin Control Register 0 (EPCR0) .............................................................. ........................... 132
4.13 External Pin Control Register 1 (EPCR1) .............................................................. ........................... 135
4.14 DRAM Signal Control Register (DSCR) ....... ..................................................................................... 136
4.15 Little Endian Register (LER) ............................................ ................................................................. 138
4.16 Relationship between Data Bus Widths and Control Signals ........................................................... 139
4.16.1 Bus Access with Big Endi ans ..................................................................... ................................. 141
4.16.2 Bus Access with Little End ians ............... ..................................................................................... 147
4.16.3 External Access ...................................... ..................................................................................... 151
4.16.4 DRAM Relationships ................................................................................................ .................... 155
4.17 Bus Timing ................... ............................................................................................................. ........ 159
4.17.1 Basic Read Cycle .......................................................................................................... .............. 162
4.17.2 Basic Write Cycles ...................................................................................... ...... ........................... 164
4.17.3 Read Cycles in Each Mode ........................................................................ ................................. 166
4.17.4 Write Cycles in Each Mode ............................................................................................ .............. 168
4.17.5 Read and Write Combination Cy cles ............................................. .............................................. 170
4.17.6 Automatic Wait Cycles ............................................................ ..................................................... 171
4.17.7 External Wait Cycles ................................................................................................ .................... 172
4.17.8 Usual DRAM Interface: Read .................................................................................. .................... 173
4.17.9 Usual DRAM Interface: Write ......................................................................................... .............. 175
4.17.10 Usual DRAM Read Cycles ................................... ........................................................................ 177
4.17.11 Usual DRAM Write Cycles ... ........................................................................................................ 1 79
4.17.12 Automatic Wait Cycles in Usual DRAM Interface .......................... .............................................. 181
4.17.13 DRAM Interface in High-Speed Page Mode .................................................................. .............. 182
4.17.14 Single DRAM Interface: Read .............................. ........................................................................ 185
4.17.15 Single DRAM Interface: Write ...................................................................................................... 1 86
4.17.16 Single DRAM Interface ..................................................... ........................................................... 187