xiv
Figure 4.17-12 Ex ample 5 of Write Cycle Timing Chart ................. ................................................................. 169
Figure 4.17-13 Ex ample of Read and Write Combination Cycle Timing Chart ............................................... 170
Figure 4.17-14 Ex ample of Automatic Wait Cycle Timing Chart ..................................................................... 171
Figure 4.17-15 Ex ample of External Wait Cycle Timing Chart ............. ........................................................... 172
Figure 4.17-16 Ex ample of Usual DRAM Interface Read Timing Chart .......................................................... 173
Figure 4.17-17 Ex ample of Usual DRAM Interface Write Timing Chart .......................................................... 175
Figure 4.17-18 Ex ample 1 of Usual DRAM Read Cycle Timing Chart ............................................................ 177
Figure 4.17-19 Ex ample 2 of Usual DRAM Read Cycle Timing Chart ............................................................ 178
Figure 4.17-20 Ex ample 3 of Usual DRAM Read Cycle Timing Chart ............................................................ 178
Figure 4.17-21 Ex ample 1 of Usual DRAM Write Cycle Timing Chart ............................................................ 179
Figure 4.17-22 Ex ample 2 of Usual DRAM Write Cycle Timing Chart ............................................................ 180
Figure 4.17-23 Ex ample 3 of Usual DRAM Write Cycle Timing Chart ............................................................ 180
Figure 4.17-24 Ex ample of Automatic Wait Cycle Timing Chart in Usual DRAM Interface ............................ 181
Figure 4.17-25 Example 1 of DRAM Interface Timing Chart in High-Speed Page Mode ........... .................... 182
Figure 4.17-26 Example 2 of DRAM Interface Timing Chart in High-Speed Page Mode ........... .................... 182
Figure 4.17-27 Example 3 of DRAM Interface Timing Chart in High-Speed Page Mode ........... .................... 183
Figure 4.17-28 Example 4 of DRAM Interface Timing Chart in High-Speed Page Mode ........... .................... 184
Figure 4.17-29 Ex ample of Single DRAM Interface Read Timing Chart ......................................................... 185
Figure 4.17-30 Ex ample of Single DRAM Interface Write Timing Chart ........................................... .............. 186
Figure 4.17-31 Ex ample of Single DRAM Interface Timing Chart ........................... ........................................ 187
Figure 4.17-32 Ex ample of Hyper DRAM Interface Read Timing Chart ........................ ................................. 188
Figure 4.17-33 Ex ample of Hyper DRAM Interface Write Timing Chart ............................... ........................... 189
Figure 4.17-34 Ex ample of Hyper DRAM Interface Timing Chart ................................................................... 190
Figure 4.17-35 Ex ample of CAS before RAS (CBR) Refresh Timing Chart ................................ .................... 191
Figure 4.17-36 Ex ample of Timing Chart of CBR Refresh Automatic Wait Cycle ........................................... 192
Figure 4.17-37 Exampl e of Selfrefres h Timing Chart .................................................................. ...... ..... ......... 192
Figure 4.17-38 Ex ample of Bus Control Release Timing Chart ........................................................ .............. 193
Figure 4.17-39 Ex ample of Bus Control Acquisition Timing ............................................................................ 193
Figure 4.18-1 Example of Timing Chart for 2X Clock (BW-16bit, Access-Word Read) ................................ 194
Figure 4.18-2 Example of Timing for 1X Clock (BW-16bit, Access-Word Read) ............................ .............. 195
Figure 5.1-1 Basic I/O Port Block Diagram ...................................................................... ........................... 202
Figure 6.1-1 External Interrupt/NMI Controller Registers .................................... ........................................ 212
Figure 6.1-2 External Interrupt/NMI Controller Block Diagram ...................... .............................................. 212
Figure 6.5-1 External Interrupt Operation ........................................................... ....... ...... ....... ...... . ............. 216
Figure 6.6-1 Clearing the Interrupt Cause Hold Circuit at Level Se tting for the Interrupt Request Mode ... 217
Figure 6.6-2 Input of an Interrupt Cause in Interrupt Enable Mode and a Request Issued to the Interrupt
Controller ..................................................................................................... ........................... 217
Figure 6.7-1 NMI Request Detection Block ................... .............................................................................. 218