Fujitsu FR30 - page 153

129

4.10 DRAM Control Register 4/5 (DMCR4/5)

[bit 4] REFE (REFresh Enable bit)

The REFE bit specifies whether to perform the cyclic refresh operation of the CAS before

RAS (CBR) type. When starting the cyclic refresh, regardless of areas 4 and 5, set the

REFE bit of DMCR4 or DMCR5 to "1" and set the STR bit of the refresh control register

(RFCF).

0: Does not perform a cyclic refresh (initial value).

1: Performs cyclic refresh with an interval specified by t he refresh control register (RFCR).

[bit 3] PAR (PARity select bit)

This device supports no parity function.

Setting this bit has no effect.

[bit 2] PERR (Parity ERRor bit)

This device supports no parity function.

Setting this bit has no effect.

[bit 1] PEIE (Parity Error Interrupt Enable bit)

The PEIE bit specifies whether to output an interrupt request fo r a parity error.

This device supports no parity function.

Be sure to set this bit to "0".

■Bus Width Combinations

Table 4.10.2 lists the combinations of bus widths availab le in areas 4 and 5.

Table 4.10-2 Combinations of Bus Widths Available in Areas 4 and 5

Combination Area 4 Area 5

1 Usual: 16/8 bits Usual: 16/8 bits

2 Usual: 16/8 bits DRAM: 16 bits (C/W = 0, 1)

3 Usual: 16/8 bits DRAM: 8 bits (C/W = 0, 1)

4 DRAM: 16 bits (C/W = 0, 1) Usual: 16/8 bits

5 DRAM: 16 bits (C/W = 0, 1) DRAM: 16 bits (C/W = 0, 1)

6 DRAM: 16 bits (C/W = 0, 1) DRAM: 8 bits (C/W = 0, 1)

7 DRAM: 8 bits (C/W = 0, 1) Usual: 16/8 bits

8 DRAM: 8 bits (C/W = 0, 1) DRAM: 16 bits (C/W = 0, 1)

9 DRAM: 8 bits (C/W = 0, 1) DRAM: 8 bits (C/W = 0, 1)

Contents

Main Page Page Page PREFACE Page Page iv 1999 FUJITSU LIMITED Printed in Japan How to Read This Manual Page CONTENTS CHAPTER 3 CLOCK GENERATOR AND CONTROLLER ............................................. 73 Page CHAPTER 6 EXTERNAL INTERRUPT/NMI CONTROLLER ........................................ 211 CHAPTER 7 DELAYED INTERRUPT MODULE ........................................................... 219 CHAPTER 11 A/D CONVERTER (Successive approximation type) ............................ 267 Page FIGURES Page Page Page Page TABLES Page Page Page CHAPTER 1 OVERVIEW 1.1 MB91F109 Characteristics Page Page Page 6 1.2 General Block Diagram of MB91F109 Figure 1.2.1 is a general MB91F109 block diagram. General Block Diagram of MB91F109 Figure 1.2-1 General Block Diagram of MB91F109 7 1.3 Outside Dimensions 1.3 Outside Dimensions Figures 1.3.1 to 1.3.3 show the outside dimensions of the MB91F109. Outside Dimensions (QFP-100) Figure 1.3-1 Outside Dimensions of FPT-100P-M06 8 Outside Dimensions (LQFP-100) Figure 1.3-2 Outside Dimensions of FPT-100P-M05 *QFP100-P-1414-1 (FPT-100P-M05) EIAJ code: Plastic LQFP with 100 pins Package width x length Lead shape Gull wing Sealing Plastic mold 0.50 mm 14 x 14 mm 9 Unit: mm (inches) (BGA-112P-M01) 0.80 mm 11 10.00 10.00 mm 1.45 mm MAX 0.45 (BGA-112P-M01) MB91F109 11 1.4 Pin Arrangement Diagrams Pin Arrangements (LQFP-100) Figure 1.4-2 LQFP-100 Pin Arrangements MB91F109 FPT-100P-M05 (TOP VIEW) Page Page 1.5 Pin Functions Page Page Page Page Page Page Page 1.6 I/O Circuit Format Tables 1.6.1 and 1.6.2 shows I/O circuit formats. Page 24 1.7 Memory Address Space Page 1.8 Handling of Devices This section provides notes on using devices. Page Page CHAPTER 2 CPU 2.1 CPU Architecture 2.2 Internal Architecture Page 2.3 Programming Model 34 CHAPTER 2 CPU Figure 2.3-2 Configuration of special registers 2.3.1 General-Purpose Registers 2.3.2 Special Registers Page Page 2.3.3 Program Status Register (PS) Page Page 2.4 Data Structure FR-series data is mapped as follows: Bit ordering: Little endian Byte ordering: Big endian 2.5 Word Alignment 2.6 Memory Map This section shows an MB91F109 memory map and a memory map common to the FR series. Page 2.7 Instruction Overview Page 2.7.1 Branch Instructions with Delay Slots Page Page 2.7.2 Branch Instructions without Delay Slots Instructions including branch instructions without delay slots are executed in order of coding. 2.8 EIT (Exception, Interrupt, and Trap) Page 2.8.1 EIT Interrupt Levels The EIT interrupt levels range from 0 to 31, which are managed using five bits. Page 2.8.2 Interrupt Control Register (ICR) 2.8.3 System Stack Pointer (SSP) 58 CHAPTER 2 CPU 2.8.4 Interrupt Stack 2.8.5 Table Base Register (TBR) The table base register (TBR) indicates the first address of the EIT vector table. 2.8.6 EIT Vector Table Page 2.8.7 Multiple EIT Processing Page 2.8.8 EIT Operation Page Page Page 2.9 Reset Sequence This section explains CPU resetting. 2.10 Operation Mode @@@@@@@@ Bus mode Access mode Single chip Internal-ROM-external bus External-ROM-external bus 16-bit bus width 8-bit bus width Page Page Page CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.1 Outline of Clock Generator and Controller 75 3.2 Reset Reason Resister (RSRR) and Watchdog Cycle Control Register (WTCR) Page 3.3 Standby Control Register (STCR) Page 3.4 DMA Request Suppression Register (PDRR) 3.5 Timebase Timer Clear Register (CTBR) The timebase timer clear register (CTBR) clears the timebase timer to 0 for initialization. 3.6 Gear Control Register (GCR) The gear control register (GCR) controls the gear functions of the CPU and peripheral clocks. Page Page 3.7 Watchdog Timer Reset Delay Register (WPR) 3.8 PLL Control Register (PCTR) 3.9 Gear Function Page Page 3.10 Standby Mode (Low Power Consumption Mechanism) The standby mode implies the stop state and sleep state. Page 3.10.1 Stop State Page Page 3.10.2 Sleep State Page Page 98 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10.3 Standby Mode State Transition Figure 3.10.3 is a standby mode state transition diagram. Standby Mode State Transition Figure 3.10-3 Standby Mode State Transition 3.11 Watchdog Function Page 3.12 Reset Source Hold Circuit Page 3.13 DMA Suppression Page 3.14 Clock Doubler Function Page Page 108 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.15 Example of PLL Clock Setting This section provides an example of PLL clock setting and an example of the assembler source. <Notes> The DBLO N, VSTP, and SLCT0 bits can be set in any order. Page Page CHAPTER 4 BUS INTERFACE 4.1 Outline of Bus Interface The bus interface controls the interface between external memory and I/O. Page 114 4.2 Chip Select Area A total of six types of chip select area are prepared for the bus interface. 4.3 Bus Interface Page 118 4.4 Area Select Register (ASR) and Area Mask Register (AMR) Area mask registers (AMR1 to AMR5) Page Page 4.5 Area Mode Register 0 (AMD0) Page 4.6 Area Mode Register 1 (AMD1) 4.7 Area Mode Register 32 (AMD32) 4.8 Area Mode Register 4 (AMD4) Address: 0000 DRME BW1 BW0 WTC2 WTC1 WTC0 0--00000 R/W AMD4 0623 Initial value Access 4.9 Area Mode Register 5 (AMD5) AMD5 0624 DRME BW1 BW0 WTC2 WTC1 WTC0 0--00000 R/W Address: 0000 Initial value Access 4.10 DRAM Control Register 4/5 (DMCR4/5) Page Page 4.11 Refresh Control Register (RFCR) Page 4.12 External Pin Control Register 0 (EPCR0) Page Page 4.13 External Pin Control Register 1 (EPCR1) External pin control register 1 (EPCR1) controls address signal output. 4.14 DRAM Signal Control Register (DSCR) Page 4.15 Little Endian Register (LER) 4.16 Relationship between Data Bus Widths and Control Signals Page 4.16.1 Bus Access with Big Endians Page Page Page 145 8-bit bus width Figure 4.16-9 External Bus Access for 8-bit Bus Width Page 4.16.2 Bus Access with Little Endians Page Page Page 151 4.16.3 External Access This section lists several external accesses. Word Access 16-bit bus 8-bit bus 152 Half-Word Access 16-bit bus 8-bit bus 153 Byte Access 16-bit bus 154 8-bit bus width 4.16.4 DRAM Relationships This section explains the DRAM relationships. Page Page Page 4.17 Bus Timing Page Page 4.17.1 Basic Read Cycle This section provides a chart of the basic read cycle timing. Page 4.17.2 Basic Write Cycles This section provides a chart of the basic write cycle timing. Page 4.17.3 Read Cycles in Each Mode This section provides read cycle timing charts in each mode. Page 4.17.4 Write Cycles in Each Mode This section provides write cycle timing charts in each mode. Page 4.17.5 Read and Write Combination Cycles This section provides a read and write combination cycle timing chart. 4.17.6 Automatic Wait Cycles This section provides an automatic wait cycle timing chart. 4.17.7 External Wait Cycles This section provides an external wait cycle timing chart. 4.17.8 Usual DRAM Interface: Read This section provides a usual DRAM interface read timing chart. Page 4.17.9 Usual DRAM Interface: Write This section provides a usual DRAM interface write timing chart. Page 4.17.10 Usual DRAM Read Cycles This section provides usual DRAM read cycle timing charts. Page 4.17.11 Usual DRAM Write Cycles This section provides usual DRAM write cycle timing charts. 180 Bus width: 16 bits, access: bytes Figure 4.17-22 Example 2 of Usual DRAM Write Cycle Timing Chart 4.17.12 Automatic Wait Cycles in Usual DRAM Interface This section provides an automatic wait cycle timing chart in the usual DRAM interface. 4.17.13 DRAM Interface in High-Speed Page Mode This section provides DRAM interface operation timing charts in high-speed page mode. Page Page 4.17.14 Single DRAM Interface: Read This section provides a read timing chart for a single DRAM interface. 4.17.15 Single DRAM Interface: Write This section provides a single DRAM interface write timing chart. 4.17.16 Single DRAM Interface This section provides a single DRAM interface timing chart. 4.17.17 Hyper DRAM Interface: Read This section provides a hyper DRAM interface timing chart. 4.17.18 Hyper DRAM Interface: Write This section provides a hyper DRAM interface write timing chart. 4.17.19 Hyper DRAM Interface This section provides a hyper DRAM interface timing chart. 4.17.20 DRAM Refresh This section provides DRAM refresh timing charts. Page 4.17.21 External Bus Request This section provides external bus request timing charts. 4.18 Internal Clock Multiplication (Clock Doubler) 195 4.19 Program Example for External Bus Operation This section provides a simple program example for exte rnal bus operation. Page Page Page Page Page 5.1 Outline of I/O Ports 203 5.2 Port Data Register (PDR) 5.2 Port Data Register (PDR) Configuration of Port Data Register (PDR) The port data register (PDR) is configured as follows: 204 CHAPTER 5 I/O PORTS 5.3 Data Direction Register (DDR) 5.4 Using External Pins as I/O Ports Page Page Page Page Page Page 6.1 Overview of External Interrupt/NMI Controller 6.2 Enable Interrupt Request Register (ENIR) 6.3 External Interrupt Request Register (EIRR) 6.4 External Level Register (ELVR) The external level register (ELVR) selects the request detection mode. 6.5 External Interrupt Operation 6.6 External Interrupt Request Levels 6.7 Nonmaskable Interrupt (NMI) Operation Page 7.1 Overview of Delayed Interrupt Module bit7 6543210 Address:00000430 DLYI DICR 7.2 Delayed Interrupt Control Register (DICR) The delayed interrupt control register (DICR) is used to control delayed interrupts. 7.3 Operation of Delayed Interrupt Module CHAPTER 8 INTERRUPT CONTROLLER 8.1 Overview of Interrupt Controller The interrupt controller accepts interrupts and performs arbitration over them. 225 226 CHAPTER 8 INTERRUPT CONTROLLER Figure 8.1-2 Interrupt Controller Registers (2/2) 227 8.2 Interrupt Controller Block Diagram 8.2 Interrupt Controller Block Diagram Figure 8.2-1 is an interrupt controller block diagram. Interrupt Controller Block Diagram Figure 8.2-1 Block Diagram of the Interrupt Controller 8.3 Interrupt Control Register (ICR) Page 8.4 Hold Request Cancel Request Level Setting Register (HRCL) The HRCL register is used to set the interrupt level for issuing a hold request cancel request. 8.5 Priority Check Page Page 8.6 Returning from the Standby Mode (Stop/Sleep) 8.7 Hold Request Cancel Request @ Interrupt level set in the HRCL register Interrupt level after priority check No cancel request is issued 8.8 Example of Using the Hold Request Cancel Request Function (HRCR) Page Page Page 9.1 Overview of U-TIMER 9.2 U-TIMER Registers Page 9.3 U-TIMER Operation This section explains how to calculate the U-TIMER baud rate and also explains the cascade mode. Page CHAPTER 10 UART 10.1 Overview of UART 247 10.2 Serial Mode Register (SMR) R/W R/W W R/W R/W 000027 MD1 MD0 CS0 SCKE SOE 00--0-00 Address: 000023 Page 10.3 Serial Control Register (SCR) The serial control register (SCR) controls the transfer protocol used for serial communication. Initial value 000026 PEN P SBL CL A/D REC RXE TXE 00000100 Page 10.4 Serial Input Data Register (SIDR) and Serial Output Data Register (SODR) 10.5 Serial Status Register (SSR) The serial status register (SSR) consists of flags that show the UART operating status. Page 10.6 UART Operation Page 10.7 Asynchronous (Start-Stop) Mode 10.8 CLK Synchronous Mode Page 10.9 UART Interrupt Occurrence and Flag Setting Timing Page Page 10.10Notes on Using the UART and Example for Using the UART This section provides an example for use of the UART and notes on using the UART. 264 CHAPTER 10 UART Figure 10.10-2 Communication Flowchart for Mode 1 10.11Setting Examples of Baud Rates and U-TIMER Reload Values Page Page 11.1 Overview of A/D Converter (Successive Approximation Type) The A/D converter converts analog input voltage to digital values. Page 11.2 Control Status Register (ADCS) Page Page Page Page 11.3 Data Register (ADCR) The data register (ADCR) is used to store a digital value that is the conversion result. 11.4 A/D Converter Operation Page 11.5 Conversion Data Protection Function Page 11.6 Notes on Using the A/D Converter This section provides notes on using the A/D converter Page 12.1 Overview of 16-bit Reload Timer Page 12.2 Control Status Register (TMCSR) Page 12.3 16-Bit Timer Register (TMR) and 16-Bit Reload Register (TMRLR) 12.4 Operation of 16-Bit Reload Timer 288 CHAPTER 12 16-BIT RELOAD TIMER Figure 12.4-2 Underflow Operation Timing 289 12.5 Counter States 12.5 Counter States Counter States Figure 12.5-1 Counter States Transition Page Page 13.1 Overview of the Bit Search Module 13.2 Bit Search Module Registers Page 13.3 Bit Search Module Operation and Save/Restore Processing Page Page Page CHAPTER 14 PWM TIMER 14.1 Overview of PWM Timer Page 14.2 PWM Timer Block Diagram Page 14.3 Control Status Register (PCNH, PCNL) Page Page Page 14.4 PWM Cycle Setting Register (PCSR) 14.5 PWM Duty Cycle Setting Register (PDUT) 14.6 PWM Timer Register (PTMR) The PWM timer register (PTMR) is used to read the value of the 16-bit decrementing counter. 14.7 General Control Register 1 (GCN1) The general control register 1 (GCN1) is used to select the source of PWM timer trigger input. Page Page 14.8 General Control Register 2 (GCN2) The general control register 2 (GCN2) is used for generating a start trigger by software. 14.9 PWM Operation PWM operation outputs pulses continuously. Page 14.10One-Shot Operation One-shot operation outputs a single pulse. Page 14.11Interrupt Figure 14.11-1 shows the causes of interrupts and their timing. 14.12Constant "L" or Constant "H" Output from PWM Timer 14.13Starting Multiple PWM Timer Channels Page CHAPTER 15 DMAC 15.1 Overview of DMAC The DMAC is a built-in module of the MB91F109 that i mplement s direct me mory access (DMA). Page 15.2 DMAC Parameter Descriptor Pointer (DPDP) 15.3 DMAC Control Status Register (DACSR) Page 15.4 DMAC Pin Control Register (DATCR) Page Page 15.5 Descriptor Register in RAM Page Page 15.6 DMAC Transfer Modes Page Page 15.7 Output of Transfer Request Acknowledgment and Transfer End signals 15.8 Notes on DMAC This section provides notes on using the DMAC. Page Page 15.9 DMAC Timing Charts 343 15.9.1 Timing Charts of the Descriptor Access Block Required pin input mode: level, descriptor address: internal This section shows timing charts of the descriptor access block. Descriptor Access Block Required pin input mode: level, descriptor address: external Page 345 15.9.2 Timing Charts of Data Transfer Block Transfer source area: external, transfer destination area: e xternal RAM This section shows timing charts of the data transfer block. Page 347 15.9.3 Transfer Stop Timing Charts in Continuous Transfer Mode This section shows transfer stop timing charts in continuous transfer mode. Transfer source area: external, transfer destination area: int ernal RAM 348 Transfer source area: external, transfer destination area: internal RAM 349 15.9.4 Transfer Termination Timing Charts Bus width: 16 bits, data length: 32 bits This section shows transfer termination timing charts. 350 Transfer Termination (When Both Addresses are Changed.) Bus width: 16 bits, data length: 8/16 bits Bus width: 16 bits, data length: 32 bits CHAPTER 16 FLASH MEMORY 16.1 Outline of Flash Memory Page 16.2 Block Diagram of Flash Memory Figure 16.2-1 is a block diagram of the flash memory. 16.3 Flash Memory Status Register (FSTR) Page 357 16.4 Sector Configuration of Flash Memory 16.4 Sector Configuration of Flash Memory Page 16.5 Flash Memory Access Modes Page 16.6 Starting the Automatic Algorithm Page Page 16.7 Execution Status of the Automatic Algorithm (Undefined) Page Page Page Page APPENDIX APPENDIX A I/O Maps Page Page Page Page Page Page Page Page APPENDIX B Interrupt Vectors Page Page Page APPENDIX C Pin Status for Each CPU Status 384 Pin Status for Each CPU Status Table C-2 Pin Status for 16-bit External Bus Length and 2CA1WR Mode 385 Table C-2 Pin Status for 16-bit External Bus Length and 2CA1WR Mode (Continued) Page 387 Table C-3 Pin Status for 16-bit External Bus Length and 2CA1WR Mode 388 Table C-3 Pin Status for 16-bit External Bus Length and 2CA1WR Mode (Continued) Page 390 Table C-4 Pin Status in 8-bit External Bus Mode 391 Table C-4 Pin Status in 8-bit External Bus Mode (Continued) Page 393 Table C-5 Pin Status in Single Chip Mode 394 P: when a general-purpose port is specified, F: when the spec ified function is selected Table C-5 Pin Status in Single Chip Mode (Continued) Page D.1 C Compiler (fcc911) 01 02 03 04 01 02 03 04 (Big endian area) (Little endian area) (Correct result) memcpy 01 020304 Page D.2 Assembler (fsm911) Page D.3 Linker (flnk911) D.4 Debuggers (sim911, eml911, and mon911) This section provides notes on the simulator debugger and emulator or monitor debugger. APPENDIX E Instructions Page Page Page Page Page E.1 FR-Series Instructions This section describes the FR-series instructions in the following order: Page Page Page Page Page 415 Standard Branch (Without Delay) Instructions Table E.1-11 Standard Branch (Without Delay) Instructions 416 Delayed-Branch Instructions Table E.1-12 Delayed Branch Instructions BV:D label9 BNV:D label9 BHI:D label9 417 Other Instructions Table E.1-13 Other Instructions Page Page Page Page Page Page Page Page Index