Commands without data transfer | Fujitsu MHA2021AT, MHA2032AT

5.4 Command Protocol

Note:

For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 μs after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred. If the timing to read the Status register does not meet above condition, normal data transfer operation is not assured guaranteed.

When the host issues the command even if the drive requests the data transfer (DRQ bit is set), or when the host executes resetting, the device correct operation is not guaranteed.

5.4.3 Commands without data transfer

Execution of the following commands does not involve data transfer between the host and the device.

∙

∙

∙

∙

∙

∙

∙

∙

∙

∙

∙

∙

∙

∙

RECABLIBRATE

SEEK

READY VERIFY SECTOR(S)

EXECUTE DEVICE DIAGNOSTIC

INITIALIZE DEVICE PARAMETERS

SET FEATURES

SET MULTIPLE MODE

IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

CHECK POWER MODE

SECURITY ERASE PREPARE

SECURITY FREEZE LOCK

Figure 5.6 shows the protocol for the command execution without data transfer.

Figure 5.6 Protocol for the command execution without data transfer

C141-E042-01EN

5-73

Image 134

Fujitsu MHA2021AT, MHA2032AT manual Commands without data transfer, Protocol for the command execution without data transfer

Contents

MHA2021AT, MHA2032AT Disk Drives Product Manual For Safe Operation Handling of This Manual Revision History Preface Overview of Manual Abbreviation Conventions for Alert MessagesOperating Environment Liability Exception Important Alert Items Important Alert Messages Contents Contents Interface IN-1 GL-1AB-1 Illustrations Figures Tables C141-E042-01EN Xiii Device Overview Adaptability FeaturesFunctions and performance Interface Features Specifications Device SpecificationsSpecifications summary MHA2021AT MHA2032AT MHA2021AT Power RequirementsModel and product number Model names and product numbers Current and power dissipation Current fluctuation Typ. at +5V when power is turned on Acoustic noise specification Environmental SpecificationsEnvironmental specifications Acoustic Noise Reliability Shock and vibration specificationShock and Vibration MTBF= Error Rate Media Defects Device Configuration Device Configuration Disk drive outerview MHA2021ATMHA2032AT 2 1 drive connection System ConfigurationATA interface 2 drives configuration 3 2 drives connection Installation Conditions Dimensions Dimensions Mounting Orientation PCA Mounting frame structure Measurement point Temperature DE cover Service area Device connector Cable Connections Device connection Cable connector specificationsCable connector specifications Berg Location of setting jumpers Jumper SettingsPower supply connector CN1 Factory default setting Master drive-slave drive setting Csel setting 13 Example 1 of Cable Select 14 Example 2 of Cable Select Theory of Device Operation Disk OutlineSubassemblies Head Air filter SpindleActuator Circuit Configuration Circuit Configuration Power-on Sequence Self-calibration contents Self-calibration Execution timing of self-calibration Read/write Circuit Command processing during self-calibrationSelf-calibration execution timechart Read/write preamplifier PreAMP Write circuit Write precompensation algorithm Read/write circuit block diagram Frequency characteristic of programmable filter Read circuit Time base generator circuit Write clock freqeuncy and recording density BPI of each zone Servo Control Servo control circuit Servo Control Physical sector servo configuration on disk surface Servo Control Data-surface servo format Servo frame format Actuator motor control Spindle motor control Servo Control Interface Physical Interface Interface signalsSignal assignment on the connector Encsel Signal assignment on the interface connectorDasp GND MSTR, I, Master/slave setting Pidag Dasp Logical Interface 1 I/O registers I/O registers DA2 DA1 DA0 Command block registers Icrc UNC Logical Interface DEV HS3 HS2 HS1 HS0 ERR BSYDSC DRQ Interface Srst Host CommandsControl block registers Command code and parameters Command code and parameters 1 Command code and parameters 2 Command descriptions Host Commands MSB Read Multiple X’C4’ Host Commands Execution example of Read Multiple command Host Commands Interface Host Commands 1F7 HCM 1F6 HDH Start head No. /LBA Write Multiple X’C5’ Start head No. /LBA Write Verify X’3C’ Interface Host Commands Initialize Device Parameters X’91’ Identify Device X’EC’ Information to be read by Identify Device command 1 Word Value Description Information to be read by Identify Device Command 2 Host Commands Information to be read by Identify Device Command 3 Identify Device DMA X’EE’ SET Features X’EF’ Features register values and settable modes Host Commands SET Multiple Mode X’C6’ Host Commands Execute Device Diagnostic X’90’ Diagnostic code Interface Host Commands Write Buffer X’E8’ Host Commands ’97’ or X’E3’ ’95’ or X’E1’ ’96’ or X’E2’ At command issuance I/O registers setting contents 1F7 HCM ’FF’ ’98’ or X’E5’ Features Register values subcommands and functions Smart Return Status Format of device attribute value data 1FF Format of insurance failure threshold value data Interface 10 Contents of security password Interface Host Commands Interface ∙ Read Sectors ∙ Write Sectors ∙ Write Vetif 11 Contents of Security SET Password data Cancel Locked Mode Interface Error posting 13 Command code and parameters 1 13 Command code and parameters 2 Execute Device Diagnostic Initialize Device Parameters Command ProtocolData transferring commands from device to host Read Sectors command protocol Data transferring commands from host to device Protocol for command abort Write Sectors command protocol Commands without data transfer Protocol for the command execution without data transfer Read Multiple Sleep Write Multiple Other commandsDMA data transfer commands Read DMA Write DMA Normal DMA data transfer Timing PIO data transfer Data transfer timing Single word DMA data transfer timing mode Single word DMA data transfer Power-on and reset Multiword DMA data transfer 11 Power on Reset Timing Operations Device Response to the Reset Response to power-on Response to power-on Response to hardware reset Response to hardware reset Response to software reset Response to software reset Response to diagnostic command Response to diagnostic command Address Translation Default parametersDefault parameters Address translation example in CHS mode Logical address Power Save Power save mode Operations Power commands Defect Management Spare area Alternating defective sectors Alternate cylinder assignment Caching operation Data buffer configurationRead-Ahead Cache − Read Sector S − Read DMA Read Sector S Read Multiple Read DMA− Write Sectors − Write DMA − Write Multiple Usage of read segment Following shows the cache enabled data for next read command HAP DAP Read-ahead data New read-ahead data Hit data Finally, the cache data in the buffer is as follows Last LBA Write Cache Write Cache Glossary PIO Programmed input-output Power save modeRotational delay Positioning Status VCM Acronyms and Abbreviations Index Index Initialize Device Parameters Index SET Features IN-6 C141-E042-01EN Japan Comment FormMHA2021AT, MHA2032AT Disk Drives Product Manual C141-E042-01EN