Host Commands, Control block registers, Srst | Fujitsu MHA2021AT

5.3 Host Commands

5.2.3 Control block registers

(1) Alternate Status register (X’3F6’)

The Alternate Status register contains the same information as the Status register of the command block register.

The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit	1	Bit 0

BSY	DRDY	DF	DSC	DRQ	CORR	0		ERR

(2) Device Control register (X’3F6’)

The Device Control register contains device interrupt and software reset.

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit	0

X	X	X	X	X	SRST	nIEN	0

-Bit 2: SRST is the host software reset bit. When this bit is set, the device is held reset state. When two device are daisy chained on the interface, setting this bit resets both device simultaneously.

The slave device is not required to execute the DASP- handshake.

-Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When this bit is 0 and the device is selected, an interruption (INTRQ signal) can be enabled through a tri-state buffer. When this bit is 1 or the device is not selected, the INTRQ signal is in the high- impedance state.

5.3Host Commands

The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the Command register.

The device can accept the command when the BSY bit is 0 (the device is not in the busy status).

The host system can halt the uncompleted command execution only at execution of hardware or software reset.

C141-E042-01EN

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Fujitsu MHA2021AT, MHA2032AT manual Host Commands, Control block registers, Srst

Contents

MHA2021AT, MHA2032AT Disk Drives Product Manual For Safe Operation Handling of This Manual Revision History Preface Overview of Manual Abbreviation Conventions for Alert MessagesOperating Environment Liability Exception Important Alert Items Important Alert Messages Contents Contents Interface IN-1 GL-1AB-1 Illustrations Figures Tables C141-E042-01EN Xiii Device Overview Adaptability FeaturesFunctions and performance Interface Features Specifications Device SpecificationsSpecifications summary MHA2021AT MHA2032AT MHA2021AT Power RequirementsModel and product number Model names and product numbers Current and power dissipation Current fluctuation Typ. at +5V when power is turned on Acoustic noise specification Environmental SpecificationsEnvironmental specifications Acoustic Noise Reliability Shock and vibration specificationShock and Vibration MTBF= Error Rate Media Defects Device Configuration Device Configuration Disk drive outerview MHA2021ATMHA2032AT 2 1 drive connection System ConfigurationATA interface 2 drives configuration 3 2 drives connection Installation Conditions Dimensions Dimensions Mounting Orientation PCA Mounting frame structure Measurement point Temperature DE cover Service area Device connector Cable Connections Device connection Cable connector specificationsCable connector specifications Berg Location of setting jumpers Jumper SettingsPower supply connector CN1 Factory default setting Master drive-slave drive setting Csel setting 13 Example 1 of Cable Select 14 Example 2 of Cable Select Theory of Device Operation Disk OutlineSubassemblies Head Air filter SpindleActuator Circuit Configuration Circuit Configuration Power-on Sequence Self-calibration contents Self-calibration Execution timing of self-calibration Read/write Circuit Command processing during self-calibrationSelf-calibration execution timechart Read/write preamplifier PreAMP Write circuit Write precompensation algorithm Read/write circuit block diagram Frequency characteristic of programmable filter Read circuit Time base generator circuit Write clock freqeuncy and recording density BPI of each zone Servo Control Servo control circuit Servo Control Physical sector servo configuration on disk surface Servo Control Data-surface servo format Servo frame format Actuator motor control Spindle motor control Servo Control Interface Physical Interface Interface signalsSignal assignment on the connector Encsel Signal assignment on the interface connectorDasp GND MSTR, I, Master/slave setting Pidag Dasp Logical Interface 1 I/O registers I/O registers DA2 DA1 DA0 Command block registers Icrc UNC Logical Interface DEV HS3 HS2 HS1 HS0 ERR BSYDSC DRQ Interface Srst Host CommandsControl block registers Command code and parameters Command code and parameters 1 Command code and parameters 2 Command descriptions Host Commands MSB Read Multiple X’C4’ Host Commands Execution example of Read Multiple command Host Commands Interface Host Commands 1F7 HCM 1F6 HDH Start head No. /LBA Write Multiple X’C5’ Start head No. /LBA Write Verify X’3C’ Interface Host Commands Initialize Device Parameters X’91’ Identify Device X’EC’ Information to be read by Identify Device command 1 Word Value Description Information to be read by Identify Device Command 2 Host Commands Information to be read by Identify Device Command 3 Identify Device DMA X’EE’ SET Features X’EF’ Features register values and settable modes Host Commands SET Multiple Mode X’C6’ Host Commands Execute Device Diagnostic X’90’ Diagnostic code Interface Host Commands Write Buffer X’E8’ Host Commands ’97’ or X’E3’ ’95’ or X’E1’ ’96’ or X’E2’ At command issuance I/O registers setting contents 1F7 HCM ’FF’ ’98’ or X’E5’ Features Register values subcommands and functions Smart Return Status Format of device attribute value data 1FF Format of insurance failure threshold value data Interface 10 Contents of security password Interface Host Commands Interface ∙ Read Sectors ∙ Write Sectors ∙ Write Vetif 11 Contents of Security SET Password data Cancel Locked Mode Interface Error posting 13 Command code and parameters 1 13 Command code and parameters 2 Execute Device Diagnostic Initialize Device Parameters Command ProtocolData transferring commands from device to host Read Sectors command protocol Data transferring commands from host to device Protocol for command abort Write Sectors command protocol Commands without data transfer Protocol for the command execution without data transfer Read Multiple Sleep Write Multiple Other commandsDMA data transfer commands Read DMA Write DMA Normal DMA data transfer Timing PIO data transfer Data transfer timing Single word DMA data transfer timing mode Single word DMA data transfer Power-on and reset Multiword DMA data transfer 11 Power on Reset Timing Operations Device Response to the Reset Response to power-on Response to power-on Response to hardware reset Response to hardware reset Response to software reset Response to software reset Response to diagnostic command Response to diagnostic command Address Translation Default parametersDefault parameters Address translation example in CHS mode Logical address Power Save Power save mode Operations Power commands Defect Management Spare area Alternating defective sectors Alternate cylinder assignment Caching operation Data buffer configurationRead-Ahead Cache − Read Sector S − Read DMA Read Sector S Read Multiple Read DMA− Write Sectors − Write DMA − Write Multiple Usage of read segment Following shows the cache enabled data for next read command HAP DAP Read-ahead data New read-ahead data Hit data Finally, the cache data in the buffer is as follows Last LBA Write Cache Write Cache Glossary PIO Programmed input-output Power save modeRotational delay Positioning Status VCM Acronyms and Abbreviations Index Index Initialize Device Parameters Index SET Features IN-6 C141-E042-01EN Japan Comment FormMHA2021AT, MHA2032AT Disk Drives Product Manual C141-E042-01EN