5.3 Host Commands
This command is operated under the following conditions:
∙The command is issued in a sequence of the READ LONG or WRITE LONG (to the same address) command issuance. (WRITE LONG command can be continuously issued after the READ LONG command.)
If above condition is not satisfied, the command operation is not guaranteed.
At command issuance (I/O registers setting contents)
1F7H(CM) | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | R |
1F6H(DH) | × | L | × | DV |
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1F5H(CH) | Cylinder No. [MSB] / LBA |
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1F4H(CL) | Cylinder No. [LSB] / LBA |
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1F3H(SN) | Sector No. / LBA [LSB] |
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1F2H(SC) | 01 |
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1F1H(FR) | xx |
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R= 0 →with Retry R = 1 →without Retry
At command completion (I/O registers contents to be read)
1F7H(ST) | Status information |
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1F6H(DH) | × |
| L | × | DV | Head No. /LBA [MSB] |
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1F5H(CH) | Cylinder No. [MSB] / LBA | |||||
1F4H(CL) | Cylinder No. [LSB] / LBA | |||||
1F3H(SN) | Sector No. / LBA [LSB] | |||||
1F2H(SC) | 00 (*1) |
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1F1H(ER) | Error information |
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*1 If the command is terminated due to an error, this register indicates 01.
(19) READ BUFFER (X’E4’)
The host system can read the current contents of the sector buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up the sector buffer for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer.
