Fujitsu MHA2032AT Other commands, DMA data transfer commands, Read Multiple Sleep Write Multiple

Models: MHA2032AT MHA2021AT

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Interface

5.4.4 Other commands

READ MULTIPLE

SLEEP

WRITE MULTIPLE

See the description of each command.

5.4.5 DMA data transfer commands

READ DMA

WRITE DMA

Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issurance.

Interruption processing for DMA transfer does not issue interruptions in any intermediate sector when a multisector command is executed.

The following outlines the protocol:

The interrupt processing for the DMA transfer differs the following point.

The interrupt processing for the DMA transfer differs the following point.

a)The host writes any parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head register.

b)The host initializes the DMA channel

c)The host writes a command code in the Command register.

d)The device sets the BSY bit of the Status register.

e)The device asserts the DMARQ signal after completing the preparation of data transfer. The device asserts either the BSY bit or DRQ bit during DMA data transfer.

f)When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register.

The host resets the DMA channel.

Figure 5.7 shows the correct DMA data transfer protocol.

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C141-E042-01EN

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Fujitsu MHA2032AT manual Other commands, DMA data transfer commands, Read Multiple Sleep Write Multiple, Read DMA Write DMA