CHAPTER 5 INTERFACE | 5 - 1 | ||
5.1 | Physical Interface | 5 | - 2 |
5.1.1 | Interface signals | 5 | - 2 |
5.1.2 | Signal assignment on the connector | 5 - 3 | |
5.2 | Logical Interface | 5 | - 6 |
5.2.1 | I/O registers | 5 | - 6 |
5.2.2 | Command block registers | 5 | - 8 |
5.2.3 | Control block registers | 5 | - 13 |
5.3 | Host Commands | 5 | - 13 |
5.3.1 | Command code and parameters | 5 - 14 | |
5.3.2 | Command descriptions | 5 | - 16 |
5.3.3 | Error posting | 5 | - 75 |
5.4 | Command Protocol | 5 | - 76 |
5.4.1 | Data transferring commands from device to host | 5 - 76 | |
5.4.2 | Data transferring commands from host to device | 5 - 78 | |
5.4.3 | Commands without data transfer | 5 - 80 | |
5.4.4 | Other commands | 5 | - 81 |
5.4.5 | DMA data transfer commands | 5 | - 81 |
5.5 | Ultra DMA Feature Set | 5 | - 83 |
5.5.1 | Overview | 5 | - 83 |
5.5.2 | Phases of operation | 5 | - 84 |
5.5.3 | Ultra DMA data in commands | 5 | - 84 |
5.5.3.1 | Initiating an Ultra DMA data in burst | 5 | - 84 |
5.5.3.2 | The data in transfer | 5 | - 85 |
5.5.3.3 | Pausing an Ultra DMA data in burst | 5 | - 85 |
5.5.3.4 | Terminating an Ultra DMA data in burst | 5 - 86 | |
5.5.4 | Ultra DMA data out commands | 5 | - 88 |
5.5.4.1 | Initiating an Ultra DMA data out burst | 5 | - 88 |
5.5.4.2 | The data out transfer | 5 | - 89 |
5.5.4.3 | Pausing an Ultra DMA data out burst | 5 | - 89 |
5.5.4.4 | Terminating an Ultra DMA data out burst | 5 - 90 | |
5.5.5 | Ultra DMA CRC rules | 5 | - 92 |
5.5.6 | Series termination required for Ultra DMA | 5 - 93 | |
5.6 | Timing | 5 | - 94 |
5.6.1 | PIO data transfer | 5 | - 94 |
5.6.2 | Multiword data transfer | 5 | - 95 |
ix |
