5.6.3.2 Ultra DMA data burst timing requirements
Table 5.17 Ultra DMA data burst timing requirements (1 of 2)
| MODE 0 | MODE 1 | MODE 2 | MODE 3 | MODE 4 | MODE 5 |
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NAME | (in ns) | (in ns) | (in ns) | (in ns) | (in ns) | (in ns) | COMMENT | ||||||
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| MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX |
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t2CYCTYP | 240 |
| 160 |
| 120 |
| 90 |
| 60 |
| 40 |
| Typical sustained average two |
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| cycle time |
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tCYC | 112 |
| 73 |
| 54 |
| 39 |
| 25 |
| 16.8 |
| Cycle time allowing for |
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| asymmetry and clock variations |
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| (from STROBE edge to STROBE |
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| edge) |
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t2CYC | 230 |
| 153 |
| 115 |
| 86 |
| 57 |
| 38 |
| Two cycle time allowing for clock |
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| variations (from rising edge to |
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| next rising edge or from falling |
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| edge to next falling edge of |
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| STROBE) |
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tDS | 15 |
| 10 |
| 7 |
| 7 |
| 5 |
| 4 |
| Data setup time at recipient (from |
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| data valid until STROBE edge) |
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| (*2), (*5) |
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tDH | 5 |
| 5 |
| 5 |
| 5 |
| 5 |
| 4.6 |
| Data hold time at recipient (from |
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| STROBE edge until data may |
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| become invalid) (*2), (*5) |
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tDVS | 70 |
| 48 |
| 31 |
| 20 |
| 6.7 |
| 4.8 |
| Data valid setup time at sender |
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| (from data valid until STROBE |
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| edge) (*3) |
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tDVH | 6.2 |
| 6.2 |
| 6.2 |
| 6.2 |
| 6.2 |
| 4.8 |
| Data valid hold time at sender |
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| (from STROBE edge until data |
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| may become invalid) (*3) |
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tCS | 15 |
| 10 |
| 7 |
| 7 |
| 5 |
| 5 |
| CRC word setup time at device |
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| (*2) |
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tCH | 5 |
| 5 |
| 5 |
| 5 |
| 5 |
| 5 |
| CRC word hold time device (*2) |
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tCVS | 70 |
| 48 |
| 31 |
| 20 |
| 6.7 |
| 10 |
| CRC word valid setup time at host |
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| (from CRC valid until DMACK- |
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| negation) (*3) |
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tCVH | 6.2 |
| 6.2 |
| 6.2 |
| 6.2 |
| 6.2 |
| 10 |
| CRC word valid hold time at |
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| sender (from |
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| until CRC may become invalid) |
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| (*3) |
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tZFS | 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 35 |
| Time from STROBE output |
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| transition of critical timing |
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tDZFS | 70 |
| 48 |
| 31 |
| 20 |
| 6.7 |
| 25 |
| Time from data output |
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| driving until the first transition of |
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| critical timing |
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tFS |
| 230 |
| 200 |
| 170 |
| 130 |
| 120 |
| 90 | First STROBE time (for device to |
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| first negate DSTROBE from |
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| STOP during a data in burst) |
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tLI | 0 | 150 | 0 | 150 | 0 | 150 | 0 | 100 | 0 | 100 | 0 | 75 | Limited interlock time (*1) |
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tMLI | 20 |
| 20 |
| 20 |
| 20 |
| 20 |
| 20 |
| Interlock time with minimum (*1) |
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TUI | 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| Unlimited interlock time (*1) |
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| 5 - 97 |