Write DMA CAh/CBh | Hitachi HTS543212L9SA00, HTS543280L9A300

The sector number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

The cylinder number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)

The head number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

163

The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs.

5K320 SATA OEM Specification

14.44Write DMA (CAh/CBh)

Command Block Output Registers

Command Block Input Registers

Register

7

6

5

4

3

2

1

0

Register

7

6

5

4

3

2

1

0

Data

-

-

-

-

-

-

-

-

Data

-

-

-

-

-

-

-

-

Feature

-

-

-

-

-

-

-

-

Error

...See Below...

Sector Count

V

V

V

V

V

V

V

V

Sector Count

V

V

V

V

V

V

V

V

LBA Low

V

V

V

V

V

V

V

V

LBA Low

V

V

V

V

V

V

V

V

LBA Mid

V

V

V

V

V

V

V

V

LBA Mid

V

V

V

V

V

V

V

V

LBA High

V

V

V

V

V

V

V

V

LBA High

V

V

V

V

V

V

V

V

Device

-

L

-

-

H

H

H

H

Device

-

-

-

-

H

H

H

H

Command

1

1

0

0

1

0

1

R

Status

...See Below...

Error Register

7	6	5	4	3	2	1	0
CRC	UNC	0	IDN	0	ABT	T0N	AM
							N
V	0	0	V	0	V	0	0

Status Register

7 6 5 4 3 2 1 0 BSY RDY DF DSC DRQ COR IDX ERR

0

V

V

V

-

0

0

V

Table 128 Write DMA Command (CAh/CBh)

The Write DMA command transfers one or more sectors of data from the host to the device, then the data is written to the disk media.

The sectors of data are transferred through the Data Register 16 bits at a time.

The host initializes a slave-DMA channel prior to issuing the command. Data transfers are qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one interrupt per command to indicate that data transfer has terminated and status is available. If an uncorrectable error occurs, the write will be terminated at the failing sector.

Output Parameters To The Device

Sector Count	The number of continuous sectors to be transferred. If zero is specified, then 256 sectors
	will be transferred.
LBA Low	The sector number of the first sector to be transferred. (L=0)
	In LBA mode, this register contains LBA bits 0 - 7. (L=1)
LBA High/Mid	The cylinder number of the first sector to be transferred. (L=0)
	In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High).
	(L=1)
H	The head number of the first sector to be transferred. (L=0)
	In LBA mode, this register contains LBA bits 24 - 27. (L=1)
R	The retry bit, but this bit is ignored.

Input Parameters From The Device

Sector Count

LBA Low

LBA High/Mid

H

Image 163

Hitachi HTS543212L9SA00, HTS543280L9A300 manual Write DMA CAh/CBh, Output Parameters To The Device Sector Count

Contents

Hitachi Travelstar 5K320 Copyright Hitachi Global Storage Technologies Table of Contents 11.6 List of Tables List of Figures 5K320 Sata OEM Specification 5K320 Sata OEM Specification 5K320 Sata OEM Specification Abbreviations General Introduction EEC PIO References Drive handling precautionsGeneral caution Outline of the drive Part 1 Functional Specification Fixed disk subsystem description Head disk assembly dataControl Electronics Formatted capacity by model number Fixed disk characteristicsFormatted capacity by model number Cylinder allocation Data sheetData sheet Cylinder allocation Command overhead Performance characteristicsPerformance characteristics Average latency Mechanical positioningAverage seek time including settling Full stroke seek Drive ready time Drive ready time Operating mode Mode transition timeOperating mode at power on Adaptive power save control Write Cache Data loss on power offWrite safety Data integrity Data buffer test Error recoveryAutomatic reallocation ECC Corrosion test SpecificationTemperature and humidity Environment Conductive noise Radiation noiseMagnetic flux density limits Requirements DC power requirements Power consumption efficiency Power consumption efficiency Failure prediction S.M.A.R.T Service life and usage conditionReliability Data reliability Load/unload Preventive maintenanceRequired Power-Off Sequence Power switch design considerations Test considerations Mounting hole locations Mechanical specificationsPhysical dimensions and weight Physical dimensions and weight Mounting orientation Connector descriptionLoad/unload mechanism Swept sine vibration Vibration and shockOperating vibration Random vibration Operating shock Nonoperating vibrationNonoperating shock Discrete tone penalty Sound power levelWeighted sound power Acoustics Electromagnetic compatibility Identification labels Packaging SafetySubstance restriction requirements Interface connector Electrical interface specificationsCabling 2 RX+ / RX Signal definitionsInterface connector pins and I/O signals 1 TX+ / TX 5K320 Sata OEM Specification M R E S E T / C O M in IT M W a K E Out of band signaling 5K320 Sata OEM Specification Part 2 Interface Specification Interrupt request Device or Host GeneralIntroduction Terminology Physical Interface Deviations from StandardRegisters Register naming convention and correspondence Command registerRegister naming convention Device Control Register Device Register Error RegisterFeatures Register Error Register Sector Count Register LBA High RegisterLBA Low Register LBA Mid Register Corr COR Register Initialization Reset ResponseReset Response Table General Operation Descriptions Reset error register values Diagnostic and Reset considerationsDefault Register Values Diagnostic Codes Emergency unload Power-off considerationsRequired power-off sequence Device’s behavior by ATA commands LBA Addressing Mode Sector Addressing ModePower Management Feature Logical CHS Addressing Mode Interface Capability for Power Modes Power ModePower Management Commands Standby/Sleep command completion timing Low Power Idle mode Initial Power Mode at Power OnPerformance Idle mode Active Idle mode Attributes Interface Power Management Mode Slumber and Partial12.8 S.M.A.R.T. Function Transition Time Security Mode Feature Set Operation example PasswordMaster Password Revision Code Security Level Initial Setting Operation from POR after User Password is set Usual Operation User Password Lost Attempt limit for Security Unlock command Command Table Command table for device lock operation Protected Area Function Able 36 Command table for device lock operationRead Native Max Address ‘F8’h Set Max Address ‘F9’h Shipping HDDs from HDD manufacturer Example for operation In LBA mode Set Max Set Password data content Set Max security extension commands Write Cache Function Seek OverlapReassign Function Recovered read errors 12.14 48-bit Address Feature SetNon recovered write errors Non recovered read errors Preserved software settings Software Setting Preservation Feature Set Smart Command Transport SCT Native Command QueuingPreserved Software Setting SCT Action Code Supported Data In Commands Command ProtocolData Out Commands Non-Data Commands First-parity DMA Commands DMA Data Transfer Commands Command set Command Descriptions + Vendor specific command Output Registers Command Set Subcommand Input Registers Check Power Mode Command E5h/98h Check Power Mode E5h/98hInput Parameters From The Device Device Configuration Overlay Command B1h Device Configuration Overlay B1hDevice Configuration Restore subcommand C0h Device Configuration Freeze Lock subcommand C1h Device Configuration SET subcommand C3h Device Configuration Identify subcommand C2h Device Configuration Overlay Data structure DCO error information definition Download Microcode 92h Download Command 92h 5K320 Sata OEM Specification Execute Device Diagnostic Command 90h Execute Device Diagnostic 90h Flush Cache E7h Flush Cache Command E7h Flush Cache Ext EAh Flush Cache EXT Command EAh Format Track 50h Vendor Specific Format Track Command 50hOutput Parameters To The Device LBA Low Format Unit F7h Vendor Specific Format Unit Command F7h Identify Device ECh Identify Device Command ECh Identify device information Identify device information 5K320 Sata OEM Specification Identify device information Identify device information Identify device information Identify device information 7AB8H =ATA8-AST 101 102 Idle E3h/97h Idle Command E3h/97hOutput Parameters To The Device Idle Immediate Command E1h/95h Unload FeatureIdle Immediate E1h/95h Initialize Device Parameters 91h Initialize Device Parameters Command 91h Read Buffer E4h Read Buffer Command E4h Read DMAC8h/C9h Read DMA Command C8h/C9hOutput Parameters To The Device Sector Count Read DMA Ext 25h Read DMA Ext Command 25h Read Fpdma Queued 60h Read Fpdma Queued Command 60hOutput Parameters To The Device Feature Current Feature Previous Log address definition Read Log Ext Command 2FhCommand Read Log Ext2Fh General purpose Log Directory Extended comprehensive Smart error log Extended comprehensive Smart error Log Error Log versionError log index Extended Error log data structure Error data structure Command data structure Extended Self-test log data structure Device error countExtended Self -test log sector Self-test log data structure revision number Extended Self-test log descriptor entry Command ErrorCommand Error information Self-test descriptor index Read Log Ext Log Page 11h Counter Reset MechanismsPhy Event Counter Counter Identifiers Phy Event Counter information Read Multiple C4h Read Multiple Command C4hInput Paramete rs From The Device Read Multiple Ext 29h Read Multiple Ext Command 29h Read Native Max Address F8h Read Native Max Address Command F8h Read Native Max Address Ext 27h Read Native Max Address Ext Command 29h Read Sectors 20h/21h Read Sectors Command 20h/21h Read Sectors Ext 24h Read Sectors Ext Command 24h Read Verify Sectors 40h/41h Read Verify Sectors Command 40h/41h Read Verify Sectors Ext 42h Read Verify Sectors Ext Command 42h Recalibrate 1xh Recalibrate Command 1xh Security Disable Password Command F6h Security Disable Password F6hPassword Information for Security Disable Password command Security Erase Prepare F3h Security Erase Prepare Command F3h Identifier Security Erase Unit Command F4hSecurity Erase Unit F4h Erase Unit Information HTS543232L9SA00 / HTS5432 32L9A300 Security Freeze Lock F5h Security Freeze Lock Command F5h Security Set Password Command F1h Security Set Password F1hSecurity Set Password Information Identifier=User / Security level = High PasswordSecurity Level Revision Code Security Unlock F2h Security Unlock Command F2hSecurity Unlock Information Seek 7xh Seek Command 7xh Sense Condition F0h vendor specific Sense Condition Command F0h Set Features Command EFh Set Features EFh Description Set Max Address F9h Set Max a ddress Command F9h SET MAX Freeze Lock 04h Set Max Address Ext 37h Set Max a ddress Ext Command 37hInput Parameters From The Device LBA Low HOB=0 142 Set Multiple C6h Set Multiple Command C6h Sleep E6h/99h Sleep Command E6h/99h M.A.R.T. Function Set Command B0h 14.40.1 S.M.A.R.T. Sub commands14.40 S.M.A.R.T Function Set B0h A.R.T. Execute Off-line Immediate Subcommand D4h A.R.T. Read Attribute Thresholds Subcommand D1hA.R.T. Enable/Disable Attribute Autosave Subcommand D2h A.R.T. Save Attribute Values Subcommand D3h LBA High ErrorStatus LBA Mid Log sector addresses A.R.T. Read Log Sector Subcommand D5hA.R.T. Write Log Sector Subcommand D6h A.R.T. Enable Operations Subcommand D8h A.R.T. Return Status Subcommand DAh A.R.T. Disable Operations Subcommand D9hA.R.T. Enable/Disable Automatic Off-Line Subcommand DBh Data Structure Revision Number Device Attributes Data StructureDevice Attribute Data Structure Individual Attribute Data Structure Individual Attribute Data StructureStatus Flag Definitions Value Definition Off-Line Data Collection StatusSelf-test execution status Bit Automatic Off-Line Data Collection Status 14.40.2.8 S.M.A.R.T. Capability Error Logging CapabilityCurrent Segment Pointer Off-Line Data Collection Capability Individual Thresholds Data Structure Device Attribute Thresholds Data StructureSelf-test completion time Data Structure Checksum Attribute Threshold 14.40.5 S.M.A.R.T. error log sector14.40.4 S.M.A.R.T. Log Directory Attribute ID Numbers Error log pointer 14.40.5.1 S.M.A.R.T. error log versionError log data structure X3h Value State X0hX1h X2h Self-test log data structure Selective self-test log data structure Error ReportingM.A.R.T. Error Codes Selective self-test log data structure Standby E2h/96h Standby Immediate E0h/94h Write Buffer E8h Write DMA CAh/CBh Write DMA Ext 35h Write DMA FUA Ext 3Dh Write Fpdma Queued 61h Sector Count Previous Write Log Ext 3Fh Write Multiple C5h Write Multiple Ext 39h Write Multiple FUA Ext CEh Write Sectors 30h/31h Write Sectors Ext 34h Write Uncorrectable Ext 45h Number of continuous sectors to be marked low order, bits Timings Comreset Erase Unit F4h on Copyright Hitachi Global Storage Technologies