The HP E1459A can be programmed to monitor channel occurrences either internally with a 1.0 MHz sample clock, or externally, with a sourced capture clock. Using either clocking technique, data channels may function as edge detect inputs and/or data capture inputs.

Events at any channel may occur simultaneously or in overlap with events on any other channel. Figure 1-2is a block diagram of the hardware interrupt resolver circuit. User software algorithms are also necessary to resolve issues of overlap and to determine the occurring sequence of events.

Figure 1-2. Resolver Block Diagram

Installing and Configuring the HP E1459A 13