the bit in the Data Available Status Register will also be unasserted. An interrupt will only occur on the backplane (IRQ) if bit 6 in the Status Register is set. The state of this bit is returned on a read of this register.

Command Register Port 0/2 (base + 10h)

b + 10h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Write

 

 

 

 

No Effect

 

DAV ENAB

INT/EXT

EDGE ENAB

 

 

 

 

 

 

 

 

 

Read

 

 

 

Always Returns FFFh

1

DAV ENAB

INT/EXT

EDGE ENAB

For reading and writing, when BS = 0 in the Status/Control Register, the data for Port 0 is accessed. When BS = 1, the data for Port 2 is accessed.

EDGE ENAB = "1" allows an edge interrupt (INTR for Port 0/2 to cause an interrupt, if enabled in the Status/Control register. When "0" edge interrupts from Port 0/2 are disabled.

INT/EXT = "0" data will be latched using the internal clock. "1" data is latched using EXT0/2 input.

DAV ENAB = "1" allows the DAV0/2 line to cause an interrupt if enabled in the Status/Control Register. The DAV line is asserted when data is latched. This should only be enabled when in external trigger mode. When set to "0" the DAV0/2 line cannot cause an interrupt.

Caution A potential hazard exists if software were to improperly program the HP E1459A to post data-capture IRQ's with the internally selected 1.0 MHz clock source. In this situation, a DAV interrupt would be posted each microsecond (if software were able to service at that rate), and would cause software to continuously vector to interrupt service upon each "return from service." Therefore, the HP E1459A should never be programmed to generate DAV interrupts with the internal clock source selected. (If bit 1 of the Command Register Word is set to a one, then bit 2 must always be set to zero.)

In the HP E1459A the Data Ready Marker is guaranteed to be cleared when the clock source is switched from internal to external. Therefore, any capture clock which occurs within the internal/external clock selection interval will not post a marker to the control FPGA and will be lost.

82 HP E1459A Register Definitions