STATus:QUEStionable:CONDition? .................................................................

66

STATus:QUEStionable:ENABle <mask> ..........................................................

66

STATus:QUEStionable:ENABle? ......................................................................

67

STATus:QUEStionable[:EVENt]? ......................................................................

67

SYSTem Subsystem ...................................................................................................

68

SYSTem:CDEScription? <number> ...................................................................

68

SYSTem:CTYPe? <number> ..............................................................................

68

SYSTem:ERRor? ................................................................................................

69

SYSTem:VERSion? ............................................................................................

69

IEEE 488.2 Common Commands...............................................................................

70

Command Quick Reference ........................................................................................

71

Appendix A

 

HP E1459A Specifications ...........................................................................................

73

Appendix B

 

HP E1459A Register Definitions ................................................................................

75

Overview.....................................................................................................................

75

Addressing the Registers ............................................................................................

76

Register Access with Logical Address ................................................................

76

Register Access with Memory Mapping .............................................................

76

Register Definitions ....................................................................................................

77

Manufacturer ID Register ....................................................................................

78

Device Type Register ..........................................................................................

78

Status/Control Register .......................................................................................

78

Edge Interrupt Status Register .............................................................................

80

Data Available Status Register ............................................................................

80

Watchdog Timer Control/Status Register ...........................................................

81

Command Register Port 0/2 ................................................................................

81

Channel Data Register Port 0/2 ...........................................................................

83

Positive Edge Detect Register Port 0/2 ...............................................................

83

Negative Edge Detect Register Port 0/2 ..............................................................

84

Positive Mask Register Port 0/2 ..........................................................................

84

Negative Mask Register Port 0/2 ........................................................................

84

Debounce Clock Register Port 0 and Port1/ Port 2 and Port 3 ...........................

85

Command Register Port 1/3 ................................................................................

86

Channel Data Register Port 1/3 ...........................................................................

87

Positive Edge Detect Register Port 1/3 ...............................................................

88

Negative Edge Detect Register Port 1/3 ..............................................................

88

Positive Mask Register Port 1/3 ..........................................................................

88

Negative Mask Register Port 1/3 ........................................................................

89

Debounce Clock Register Port 0 and Port 1/ Port 2 and Port 3 ..........................

89

Power On/Reset Conditions........................................................................................

91

Programming Examples..............................................................................................

91

Output and Edge Detection Examples ................................................................

92

Appendix C

 

Error Messages ..........................................................................................................

105

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