Input Data Capture The state of any channel, within any channel group, may be captured for subsequent processing (as data) by an externally sourced capture clock (XTRIG0N - XTRIG3N, the external trigger inputs for each port). Data channels may be interspersed among all 64 channel inputs, but the user is cautioned to ensure that all setup criteria and clock sources coincide with requirements for synchronization. (Each channel group shares a common capture clock which may not necessarily be synchronous with an external capture clock of some other channel group.)

If enabled, each register FPGA will post a "Data Available Marker" to the control FPGA on the occurrence of a corresponding capture clock. Data Available Markers are cleared by a read of the corresponding "Channel Data Register." (The static state of these markers may be tested via the "Data Available Register.") Capture clocks which occur concurrently with a "register read/marker clear" cycle, are queued and post- processed on completion of the present cycle. In that event, the marker bit is forced inactive for a two clock (16 MHz) period before again being posted to the control FPGA.

In the "Data Capture Mode", the HP E1459A may be programmed to generate an interrupt on the occurrence of an external capture clock, or an internal 1.0 MHz sample clock may be selected to allow the state of the data channels to be tested in the absence of a capture clock. Capture clock selection (internal/external) is controlled by bit 1 of the Command Register Word.

Caution A potential hazard exists if software were to improperly program the HP E1459A to post data-capture IRQ's with the internally selected 1.0 MHz clock source. In this situation, a DAV interrupt would be posted each microsecond (if software were able to service at that rate), and would cause software to continuously vector to interrupt service upon each "return from service." Therefore, the HP E1459A should never be programmed to generate DAV interrupts with the internal clock source selected.

In the HP E1459A the Data Ready Marker is guaranteed to be cleared when the clock source is switched from internal to external. Therefore, any capture clock which occurs within the internal/external clock selection interval will not post a marker to the control FPGA and will be lost.

Installing and Configuring the HP E1459A 17