Channel Data Register Port 0/2
The Channel Data Register for Port 0/2 (base + 12h) is read only. This register returns the current (last) data that has been clocked into the edge detection circuitry based on either the internal or external trigger source. If bit 4 of the Control/Status Register is low ("0"), Port 0 is accessed. If bit 4 is high ("1"), Port 2 data will be accessed.
Channel Data Register Port 0/2 (Channels
b + 12h | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Read | Ch15 | Ch14 | Ch13 | Ch12 | Ch11 | Ch10 | Ch9 | Ch8 | Ch7 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 | Ch0 |
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Read | Ch47 | Ch46 | Ch45 | Ch44 | Ch43 | Ch42 | Ch41 | Ch40 | Ch39 | Ch38 | Ch37 | Ch36 | Ch35 | Ch34 | Ch33 | Ch32 |
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Positive Edge
Detect Register Port
0/2
Channels 0 through 15 are accessed when BS = 0 in the Status/Control Register.
Channels 32 through 47 are accessed when BS = 1 in the Status/Control Register.
The Positive Edge Detect Register for Port 0/2 (base + 14h) is read only. This register captures any low to high transitions with a "1" in this register for any channel that has been enabled. A channel is enabled by setting a corresponding bit in the Positive Mask Register. Once the register is read, the data is automatically cleared. A transition is only seen if it is held long enough to pass through the debouncers. If bit 4 of the Control/Status Register is low ("0"), Port 0 data is accessed. If bit 4 is high ("1"), Port 2 data will be accessed.
Positive Edge Detect Register Port 0/2 (Channels
b + 14h | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Read | Ch15 | Ch14 | Ch13 | Ch12 | Ch11 | Ch10 | Ch9 | Ch8 | Ch7 | Ch6 | Ch5 | Ch4 | Ch3 | Ch2 | Ch1 | Ch0 |
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Read | Ch47 | Ch46 | Ch45 | Ch44 | Ch43 | Ch42 | Ch41 | Ch40 | Ch39 | Ch38 | Ch37 | Ch36 | Ch35 | Ch34 | Ch33 | Ch32 |
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For Positive/Negative Edge Detect and Mask Registers, channels 0 through 15 are accessed when BS = 0 in the Status/Control Register.
For Positive/Negative Edge Detect and Mask Registers, channels 32 through 47 are accessed when BS = 1 in the Status/Control Register.
HP E1459A Register Definitions 83