Watchdog Timer

Control/Status

Register

The Watchdog Timer Control/Status Register (base + 0Ah) can be read or written. A read of this register will automatically "pet" the Watchdog Timer and will return a "1" in bit zero when the Watchdog Timer is enabled. A "0" means the timer is disabled. Bit 2 returns the current state of the timer. If it is at "1" the timer is asserted and, if enabled, would assert SYSRESET. The timer must be "pet" periodically to keep it from asserting its output. Once the timer is unasserted and pet it will remain unasserted, as long as it is pet within its pet time. The timer is pet automatically whenever this register is read. Once the timer is unasserted, it can then be enabled. It will then assert SYSRESET if it is not pet continuously at least once within its pet time.

Watchdog Timer Control/Status Register (base + 0Ah)

b + Ah

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Write

 

 

 

 

 

 

 

No Effect

 

 

 

 

 

 

DOGENAB

 

 

 

 

 

 

 

 

 

Read

 

 

 

Always Returns FFFh

 

 

 

1

1

DOGSTATE

DOGENAB

Command Register Port 0/2

DOGENAB = "0" the watchdog timer is disabled. "1" = enabled.

DOGSTATE = "0" the watchdog timer is not asserted. "1" the watchdog timer is asserted. (If enabled when it is a "1" it will assert SYSRESET). The watchdog timer can be "pet" by doing a read of this register. The "pet" time is selected by 2 jumpers on the PC board.

The Command Register for Port 0/2 (base + 10h) can be read or written. It contains three bits used to control operating characteristics of the port. If bit 4 of the Control/Status Register is low ("0"), Port 0 is accessed. If bit 4 is high ("1"), Port 2 will be accessed. All control bits default to "0" as the reset state.

Bit 0 enables ("1") and disables ("0") an edge event to be reported in the Edge Interrupt Status Register. If this bit is "1" then any edge event captured in either the positive or negative edge detect registers will appear in the Edge Interrupt Status Register. An interrupt will only occur on the backplane (IRQ) if bit 5 in the Status Register is set. If bit 0 is set to "0" then an edge event will not be detected in the Edge Interrupt Status Register and can not cause an interrupt. When this bit is enabled the INTR line on the terminal module is active, and will be asserted as long as an edge event is captured in either edge detection register. The state of this bit is returned on a read of the register.

Bit 1 is used to select between internal and external triggering. When set to "0", the internal clock is used to latch in data. When in external trigger, the EXT input (available on the terminal module) is used to clock data into the data capture circuitry on the falling edge. The state of this bit is returned on a read of this register.

Bit 2 enables ("1") and disables ("0") an external trigger being reported in the Data Available Status Register. If this bit and bit 1 are set to "1", an external trigger will cause data to be latched into the data capture circuitry. This will cause the DAV line to be asserted and "1" to appear in the Data Available Status Register. Once read, the DAV line will be unasserted, and

HP E1459A Register Definitions 81