HP E1459A STATus Subsystem

STATus Subsystem

The STATus subsystem controls the SCPI-defined Operation and Questionable Status registers, Standard Event register, and the Status Byte register. Each is comprised of a condition register, an event register, an enable mask, and transition filters.

Note Transition filters are always set for positive edge transitions. When an event occurs, the condition is set and the event register bit is set true. If the event condition is cleared, the event status register remains set. The event status register is cleared upon reading that register.

Each status register works as follows: when a condition occurs, the appropriate bit in the condition register is set or cleared. The contents of the events register and the enable mask are logically ANDed bit-for-bit; if any bit of the result is set, the summary bit for that register is set in the status byte. The status byte summary bit for the Operation status register is bit 7; for the Questionable Signal status register, bit 3; and for the Standard Event registers is bit 5.

Syntax	STATus
	:OPERation
	:CONDition?	page 62
	:ENABle <mask>	page 62
	:ENABle?	page 63
	[:EVENt]?	page 63
	:PSUMmary:CONDition?	page 63
	:PSUMmary:ENABle <mask>	page 64
	:PSUMmary:ENABle?	page 64
	:PSUMmary[:EVENt]?	page 65
	:PRESet	page 65
	:QUEStionable
	:CONDition?	page 66
	:ENABle <mask>	page 66
	:ENABle?	page 67
	[:EVENt]?	page 67

The STATus system contains five registers, two of which are under IEEE 488.2 control: the Event Status Register (*ESE?) and the Status Byte Register (*STB?). The Operational Status bit (OPR), Service Request bit (RQS), Event Summary bit (ESB), Message Available bit (MAV) and Questionable Data bit (QUE) in the Status Byte Register (bits 7, 6, 5, 4 and 3 respectively) can be queried with the *STB? command. Use the *ESE? command to query the unmask value for the Event Status Register (the bits you want logically "OR'd" into the Summary bit). The registers are queried using decimal weighted bit values. The decimal equivalents for bits 0 through 15 are included in Figure 3-1.

Note The Questionable Status Condition, Event, and Enable registers exist for SCPI compliance only. No status bits are defined or reported in these registers.

60 HP E1459A SCPI Command Reference