Main
2 Intel NetStructure MPCBL0001 High Performance Single Board Computer
Contents
Page
Page
Page
Page
Tables
Page
Figures
Revision History
Introduction 1
1.1 Document Organization
1.2 Glossary
Page
Features Overview 2
2.1 Application
2.2 Functional Description
Intel NetStructure MPCBL0001 High Performance Single Board Computer 15
Features Overview Figure 1. Intel NetStructure MPCBL0001 SBC Block Diagram
IPMC
2.2.1 Low Voltage Intel Xeon Processor CPU-0 (U35), CPU-1 (U36)
2.2.2 Chipset
2.2.2.1 Intel E7501 Memory Controller Hub (U22)
Page
2.2.2.3 Intel 82870P2 64-bit PCI/PCI-X Controller Hub 2 (U14, U24)
2.2.3 Memory (J8, J9, J10, J11)
2.2.3.1 Memory Ordering Rule for the MCH
2.2.4 I/O
2.2.4.1 Super I/O (U28)
Page
Page
2.2.5 PMC Connector (J25, J26, J27)
2.2.6 Firmware Hub (U30, U33)
2.2.6.1 FWH 0 (Main BIOS)
2.2.6.2 FWH 1 (Backup/Recovery BIOS)
2.2.6.3 Flash ROM Backup Mechanism
2.2.7 Onboard Power Supplies
2.2.7.6 IPMB Standby Power
Hardware Management Overview 3
3.1 Sensor Data Record (SDR)
Hardware Management Overview
Table 2. Hardware Sensors (Sheet 2 of 3)
3.2 System Event Log (SEL)
Hardware Management Overview Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 1 of 4)
Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 2 of 4)
Hardware Management Overview
Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 3 of 4)
3.2.1 Temperature and Voltage Sensors
Hardware Management Overview Table 4. Sensor Thresholds for IPMC Firmware 1.0
Table 5. Sensor Thresholds for IPMC Firmware 1.2
Hardware Management Overview
Table 6. Sensor Thresholds for IPMC Firmware 1.7 and Above
Table 7. Sensor Thresholds for IPMC Firmware 1.14 and Above
3.2.2 Processor Events
3.2.3 DIMM Memory Events
3.2.4 System Firmware Progress (POST Error)
3.2.5 Critical Interrupts
Page
3.2.6 System ACPI Power State
3.2.7 IPMB Link Sensor
3.2.8 FRU Hot Swap
3.2.9 CPU Failure Detection
3.2.10 Port 80h POST Codes
3.3 Field Replaceable Unit (FRU) Information
3.4 E-Keying
3.5 IPMC Firmware Code
3.6 IPMC Firmware Upgrade Procedure
3.6.1 IPMC Firmware Upgrade Using KCS Interface
3.6.2 IPMC Firmware Upgrade via the IPMB Interface (RMCP)
3.6.2.1 Updating MPCBL0001 Firmware
3.7 OEM IPMI Commands
3.7.1 Reset BIOS Flash Type
3.7.2 Set Fibre Channel Port Selection
3.7.3 Get Fibre Channel Port Selection
3.7.4 Get HW Fibre Channel Port Selection
3.7.5 Set Control State
3.7.6 Get Control State
3.7.7 Get Port80 Data
3.8 Controls Identifier Table
3.9 Hot-Swap Process
3.9.1 Hot-Swap LED (DS10)
3.9.2 Ejector Mechanism
3.10 Interrupts and Error Reporting
3.10.1 Device Interrupts
Figure 7. Interrupt Signals
Table 22. Interrupt Assignments (Sheet 2 of 2)
3.10.2 Error Reporting
3.11 ACPI
3.11.1 System States and Power States
3.12 Reset Types
3.12.1 Reset Logic
3.12.2 Hard Reset Request
3.12.3 Soft Reset Request
3.12.4 Warm Boot
3.12.5 Cold Boot
3.12.6 Power Good
Page
Hardware Management Overview Figure 9. Reset Chain
3.13 Watchdog Timers (WDTs)
3.13.1 WDT #1
3.13.2 WDT #2
3.13.3 WDT #3
3.14 LED Status
3.14.1 Health LED
3.14.2 OOS (Out Of Service) LED
3.14.3 Hot-Swap LED
3.14.4 IDE Drive Activity LED
3.14.5 User Programmable LEDs
3.14.6 Network Link/Speed LEDs
3.14.7 Ethernet Controller Port State LEDs
3.14.8 Fibre Channel Port State LEDs
3.15 FRU Payload Control
3.15.1 Cold Reset
3.15.2 Warm Reset
3.15.3 Graceful Reboot
3.15.4 Diagnostic Interrupt
Connectors 4
Connectors Figure 14. MPCBL0001NXX SBC Front Panel
Figure 15. MPCBL0001FXX SBC Front Panel
Connectors Table 37. LED Descriptions
Table 38. Connector Assignments
4.1 Backplane Connectors
4.1.1 Power Distribution Connector (Zone 1)
4.1.2 Data Transport Connector (Zone 2)
4.1.3 Alignment Blocks
4.2 Front Panel Connectors
4.2.1 USB Connector (J12)
4.2.2 Serial Port Connector (J17)
Figure 18. Serial Port Connector (J17)
Table 42. Serial Port Connector (J17) Pin Assignments
Page
4.2.3 Fibre Channel Small Form-Factor Pluggable (SFP) Receptacle (J34 and J35)
4.2.4 Fibre Channel SFP Optical Transceiver Module
4.2.5 PMC Connectors (J25, J26, J27)
Table 45. PMC Connector Pin Assignments - 32 Bit
Connectors Table 46. PMC Connector Pin Assignments - 64 Bit
4.3 On-board Connectors
4.3.1 IDE Connector (J24)
Table 47. IDE Connector Pin Assignments
Addressing 5
5.1 Configuration Registers
5.1.1 Configuration Address Register MCH CONFIG_ADDRESS
5.1.2 Configuration Data Register MCH CONFIG_ADDRESS
5.2 I/O Address Assignments
Addressing
5.3 Memory Map
Table 51. Memory Map
5.4 IPMC Addresses
Specifications 6
6.1 Mechanical Specifications
6.1.1 Board Outline
Specifications
Figure 20. Intel NetStructure MPCBL0001 Component Layout
Specifications
Figure 21. Intel NetStructure MPCBL0001 Component Layout
AB C DEF
G
6.1.2 Backing Plate
6.1.3 Component Height
Page
Page
Page
Page
6.2 Environmental Specifications
6.3 Reliability Specifications
6.3.1 Mean Time Between Failure (MTBF) Specifications
6.3.2 Power Consumption
6.3.3 Cooling Requirements
6.4 Board Layer Specifications
6.5 Weight
BIOS Features 7
7.1 Introduction
7.2 BIOS Flash Memory Organization
7.3 Complementary Metal-Oxide Semiconductor (CMOS)
7.3.1 Copying and Saving CMOS Settings
7.4 Redundant BIOS Functionality
7.5 System Management BIOS (SMBIOS)
7.6 Legacy USB Support
7.7 BIOS Updates
7.7.1 Language Support
7.8 Recovering BIOS Data
7.9 Boot Options
7.9.1 CD-ROM and Network Boot
7.9.2 Booting without Attached Devices
7.10 Fast Booting Systems
7.10.1 Quick Boot
7.11 BIOS Security Features
BIOS Features
7.12 Remote Access Configuration
Table 56. Supervisor and User Password Functions
Table 57. Function Key Escape Code Equivalents
BIOS Setup 8
8.1 Introduction
8.2 Main Menu
8.3 Advanced Menu
8.3.1 CPU Configuration Submenu
To access this submenu, select Advanced on the menu bar, then CPU Configuration.
Table 61. Advanced Menu
BIOS Setup The submenu represented in the following table is used for configuring the CPU.
8.3.2 IDE Configuration Submenu
Table63 shows IDE device configu rati on op tion s.
To access this submenu, select Advanced on the menu bar, then IDE Configuration.
Table 62. CPU Configuration Submenu
Table 63. IDE Configuration Submenu (Sheet 1 of 2)
8.3.2.1 Primary IDE Master/Slave Submenu
Table 63. IDE Configuration Submenu (Sheet 2 of 2)
BIOS Setup Table 64. Primary IDE Master/Slave Submenu
8.3.3 Floppy Configuration Submenu
To access this submenu, select Advanced on the menu bar, then Floppy Configuration.
Tabl e 65 shows floppy device configuration options.
Table 65. Floppy Configuration Submenu
BIOS Setup
8.3.4 SuperIO Configuration Submenu
Table66 shows SuperIO config uration options.
To access this submenu, select Advanced on the menu bar, then SuperIO Configuration.
Table 66. SuperIO Configuration Submenu
8.3.5 ACPI Configuration Submenu
To access this submenu, select Advanced on the menu bar, then ACPI Configuration.
Tabl e 67 shows ACPI configuration options.
Table 67. ACPI Configuration Submenu
BIOS Setup
8.3.5.1 Advanced ACPI Configuration Submenu
Table68 shows AC PI confi guration options.
To access this submenu, select Advanced on the menu bar, then ACPI Configuration.
Table 68. Advanced ACPI Configuration Submenu
8.3.6 System Management Configuration Submenu
To access this submenu, select Advanced on the menu bar, then System Management Configuration.
Tabl e 69 shows System Management configuration options.
Table 69. System Management Configuration Submenu
BIOS Setup
8.3.7 Event Logging Configuration Submenu
Table70 shows even t logg ing configuration options.
To access this submenu, select Advanced on the menu bar, then Event Logging Configuration.
Table 70. Event Logging Configuration Submenu
8.3.8 Fibre Channel Routing (PICMG) Configuration Submenu
Tabl e 71 shows how to configure Fibre Channel routing options.
Table 71. Fibre Channel Routing (PICMG) Submenu
BIOS Setup
8.3.9 Remote Access Configuration Submenu
Table72 shows remote access configuration options.
To access this submenu, select Advanced on the menu bar, then Remote Access Configuration.
Table 72. Remote Access Configuration Submenu
8.3.10 USB Configuration Submenu
To access this submenu, select Advanced on the menu bar, then USB Configuration.
USB configuration options.
Table 73. USB Configuration Submenu
BIOS Setup
8.3.11 PCI Configuration
Table 74. USB Mass Storage Device Configuration
8.4 Boot Menu
8.4.1 Boot Settings Configuration Submenu
BIOS Setup The menu represented in the following table is used to configure Boot Settings.
8.4.2 Boot Device Priority Submenu
The menu represented in the following table is used to configure boot device priority.
To access this submenu, select Boot on the menu bar, then Boot Device Priority.
Table 77. Boot Settings Configuration Submenu
8.4.3 Hard Disk Drive Submenu
To access this submenu, select Boot on the menu bar, then Hard Disk Drive Priority.
To access this submenu, select Boot on the menu bar, then OS Load Timeout Timer.
The menu represented in the following table is used to configure hard disk drive priority.
8.4.4 OS Load Timeout Timer
8.5 Security Menu
To access this menu, select Exit from the menu bar at the top of the screen.
8.6 Exit Menu
Table 81. Security Menu
Page
Error Messages
Error Messages 9
9.1 BIOS Error Messages
The following table lists the error messages.
Table 83. BIOS Error Messages
9.2 Port 80h POST Codes
Error Messages Table 85. POST Code Checkpoints (Sheet 1 of 2)
Table 85. POST Code Checkpoints (Sheet 2 of 2)
Error Messages
The following table describes the beep codes implemented in the MPCBL0001 BIOS.
Table 86. DIM Code Checkpoints
Table 87. ACPI Runtime Checkpoints
Table 88. BIOS Beep Codes
Operating the Unit 10
10.1 BIOS Configuration
10.2 BIOS Image Updates
10.3 Procedures to Copy and Save BIOS (Including CMOS Settings)
10.3.1 Copying BIOS.bin from the SBC
10.3.2 Saving BIOS.bin to the SBC
10.3.3 Error Messages
10.4 Jumpers
Operating the Unit Table 90. J18 Pin Assignments
Table 91. J16 Jumper Assignments
Table 92. J37 Jumper assignments
10.5 Digital Ground to Chassis Ground Connectivity
Maintenance 11
11.1 Supervision
11.2 Diagnostics
11.2.1 In-Target Probe (ITP)
Thermals 12
Component Technology
Component Technology 13
Warranty Information 14
14.1 Intel NetStructure Compute Boards and Platform Products Limited Warranty
14.2 Returning a Defective Product (RMA)
14.3 For the Americas
14.3.1 For Europe, Middle East, and Africa (EMEA)
14.3.2 For Asia and Pacific (APAC)
Page
Customer Support 15
15.1 Customer Support
15.2 Technical Support and Return for Service Assistance
15.3 Sales Assistance
15.4 Product Code Summary
Certifications 16
Agency InformationClass A 17
17.1 North America (FCC Class A)
17.2 Canada Industry Canada (ICES-003 Class A) (English and French-translated)
17.3 Safety Instructions (English and French-translated)
17.3.1 English
17.4 Taiwan Class A Warning Statement
Page
Agency InformationClass B 18
18.1 North America (FCC Class B)
18.2 Canada Industry Canada (ICES-003 Class B) (English and French-translated)
18.3 Safety Instructions (English and French-translated)
18.3.1 English
18.4 Japan VCCI Class B
Page
Safety Warnings 19
19.1 Mesures de Scurit
Page
19.2 Sicherheitshinweise
Page
19.3 Norme di Sicurezza
Page
19.4 Instrucciones de Seguridad
Page
Page
Reference Documents A
Page
List of Supported Commands (IPMI v1.5 and PICMG 3.0)
List of Supported Commands (IPMI v1.5 and PICMG 3.0) B
Table 97. IPMI 1.5 Supported Commands (Sheet 1 of 3)
Table 97. IPMI 1.5 Supported Commands (Sheet 2 of 3)
List of Supported Commands (IPMI v1.5 and PICMG 3.0)
Table 97. IPMI 1.5 Supported Commands (Sheet 3 of 3)
Table 98. PICMG 3.0 IPMI Supported Commands
