Intel MPCBL0001 manual 4 I/O, Memory Ordering Rule for the MCH, Super I/O U28

Features Overview

2.2.3.1Memory Ordering Rule for the MCH

Platforms based on the E7501 chipset require DDR DIMMs to be populated in matched pairs in a specific order. Start with the two DIMMs furthest from the MCH in a “fill-farthest” approach (see Figure 2). This requirement is based on the signal integrity requirements of the DDR interface.

Figure 2. Memory Ordering

Fill Fill

Last First

MCH, U22	J9	J11
J8	J10

B0894-01

2.2.4I/O

2.2.4.1Super I/O (U28)

The Super I/O device (SIO) is an SMSC LPC47B272 enhanced Super I/O controller. The SIO connects to the ICH3 through its LPC bus connection. The SIO provides support for the front panel serial port (J17, see page 70). There is no front-panel connection to the legacy keyboard and mouse PS/2 ports. Keyboard and mouse support are provided by the USB connection (J12, see page 77). See Figure 13 for connector locations.

20	Intel NetStructure® MPCBL0001 High Performance Single Board Computer
	Technical Product Specification