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Maxim MAX12527 ______________________________________________________________________________________ 15, MAX12527, Figure 2. Functional Diagram

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MAX12527

Dual, 65Msps, 12-Bit, IF/Baseband ADC

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INBP

12-BIT

PIPELINE

ADC

DIGITAL

ERROR

CORRECTION

CHANNEL A

REFERENCE

SYSTEM

COMA

REFAN

REFAP

OVDD

DAV

OUTPUT

DRIVERS DORA

CLOCK

DIVIDER

DATA

FORMAT

12-BIT

PIPELINE

ADC

DIGITAL

ERROR

CORRECTION

OUTPUT

DRIVERS

DATA

FORMAT

DIV2

DIV4

INBN

D0B TO D11B

DORB

CHANNEL B

REFERENCE

SYSTEM

COMB

REFBN

REFBP

INAP

INAN

CLKP

CLKN

DUTY-CYCLE

EQUALIZER

CLOCK

POWER

CONTROL

AND

BIAS CIRCUITS

VDD

GND

CLOCK

REFIN INTERNAL

REFERENCE

GENERATOR

REFOUT

SHREF

DIFFCLK/SECLK

D0A TO D11A

G/T

MAX12527

Figure 2. Functional Diagram

Contents

Main MAX12527 General Description Selector Guide Ordering Information Applications MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS _______________________________________________________________________________________ 3 Page MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC _______________________________________________________________________________________ 5 Dual, 65Msps, 12-Bit, IF/Baseband ADC MAX12527 _______________________________________________________________________________________ 7 tWAKE VREFIN = 2.048V 10 ms PARAMETER SYMBOL INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE SNR, SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 65.00352MHz, AIN = -0.5dBFS) -THD, SFDR vs. ANALOG INPUT FREQUENCY (fCLK = 65.00352MHz, AIN = -0.5dBFS) SNR, SINAD vs. ANALOG INPUT AMPLITUDE SNR, SINAD vs. ANALOG INPUT AMPLITUDE -THD, SFDR vs. ANALOG INPUT AMPLITUDE SNR, SINAD vs. CLOCK SPEED -THD, SFDR vs. CLOCK SPEED SNR, SINAD vs. CLOCK SPEED -THD, SFDR vs. ANALOG SUPPLY VOLTAGE SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE -THD, SFDR vs. DIGITAL SUPPLY VOLTAGE SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE -THD, SFDR vs. DIGITAL SUPPLY VOLTAGE SNR, SINAD vs. TEMPERATURE -THD, SFDR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE OFFSET ERROR vs. TEMPERATURE Dual, 65Msps, 12-Bit, IF/Baseband ADC Pin Description Pin Description (continued) Detailed Description Pin Description (continued) ______________________________________________________________________________________ 15 MAX12527 Figure 2. Functional Diagram Analog Inputs and Input Track-and-Hold (T/H) Amplifier Reference Output Table 1. Reference Modes Clock Duty-Cycle Equalizer Clock Input and Clock Control Lines System Timing Requirements Table 2. Clock-Divider Control Inputs Table 3. Output Codes vs. Input Voltage Power-Down Input ______________________________________________________________________________________ 21 Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion Applications Information Using Transformer Coupling Single-Ended AC-Coupled Input Signal Buffered External Reference Drives Multiple ADCs MAX12527 10F0.1F ______________________________________________________________________________________ 23 Unbuffered External Reference Drives Multiple ADCs Grounding, Bypassing, and Board Layout MAX12527 Parameter Definitions Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion (IMD) 3rd-Order Intermodulation (IM3) Aperture Jitter MAX12527 Gain Matching Pin Configuration Offset Matching THIN QFN Package Information