Functional Diagram | Maxim MAX12527 manual

Dual, 65Msps, 12-Bit, IF/Baseband ADC

			CLOCK
	INAP	12-BIT	DIGITAL	DATA	OUTPUT	D0A TO D11A
		PIPELINE	ERROR	DATA	OUTPUT
		PIPELINE	ERROR	FORMAT	DRIVERS
	INAN	ADC	CORRECTION	FORMAT	DRIVERS	DORA
	INAN	ADC	CORRECTION			DORA
	REFAP	CHANNEL A
	COMA	REFERENCE	MAX12527
	REFAN	SYSTEM
	REFAN
						G/T
	REFIN		INTERNAL
			INTERNAL
	REFOUT		REFERENCE			DAV
			GENERATOR
	SHREF
	REFBP	CHANNEL B				OVDD
	REFBP	CHANNEL B
	COMB	REFERENCE
	REFBN	SYSTEM
	REFBN
	INBP	12-BIT	DIGITAL	DATA	OUTPUT	D0B TO D11B
		PIPELINE	ERROR	DATA	OUTPUT
	INBN	PIPELINE	ERROR	FORMAT	DRIVERS	DORB
		ADC	CORRECTION	FORMAT	DRIVERS
		ADC	CORRECTION
			CLOCK
	DIFFCLK/SECLK					VDD
	DIFFCLK/SECLK
	CLKP		CLOCK		POWER
					POWER
		CLOCK	DUTY-CYCLE		CONTROL	PD
		CLOCK	DUTY-CYCLE		CONTROL
		DIVIDER	EQUALIZER		AND
	CLKN	DIVIDER	EQUALIZER		AND
	CLKN				BIAS CIRCUITS
					BIAS CIRCUITS
	DIV2					GND
	DIV2
	DIV4

MAX12527

Figure 2. Functional Diagram

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Image 15

Maxim MAX12527 manual Functional Diagram

Contents

Ordering Information FeaturesGeneral Description Applications Conversion Rate Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Analog Input INAP, INAN, INBP, Inbn Parameter Symbol Conditions MIN TYP MAX Units Interchannel Characteristics Internal Reference RefoutVcom Digital Outputs D0A-D11A, D0B-D11B, DORA, DORB, DAV Parameter Symbol Conditions MIN TYPClock Inputs CLKP, Clkn Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 DIFFCLK/SECLK = GND Power RequirementsD0A-D11A, Dora Ovdd FFT Plot 32,768-POINT Data Record Typical Operating CharacteristicsTiming Characteristics Figure FFT Plot 16,384-POINT Data Record MAX12527 THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHz FIN = 70MHz, AIN = -0.5dBFSTHD, Sfdr vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS SNR, Sinad vs. Temperature fIN = 175MHz, AIN = -0.5dBFS Pin Description PIN Name FunctionSame side of the PC board D3B D0BD1B D2B Refin Detailed DescriptionShref Refout Functional Diagram Reference Output Reference ConfigurationsReference Mode Analog Inputs and Input Track-and-Hold T/H Amplifier Clock Input and Clock Control Lines Clock Duty-Cycle Equalizer DIV4 DIV2 Function System Timing Requirements D11A-D0A D11B-D0B CODE10 Equivalent BinaryD11A-D0A DOR Vrefp Vrefn Power-Down Input Binary-to-Gray and Gray-to-Binary Code Conversion Using Transformer Coupling Single-Ended AC-Coupled Input SignalApplications Information Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCs MAX12527 Grounding, Bypassing, and Board Layout Parameter Definitions Total Harmonic Distortion THD Aperture DelayFull-Power Bandwidth Overdrive Recovery Time Pin Configuration Gain MatchingOffset Matching 68L QFN THIN.EPS Package Information