Pin Configuration, Gain Matching, Offset Matching | Maxim MAX12527

Dual, 65Msps, 12-Bit, IF/Baseband ADC

Gain Matching

Gain matching is a figure of merit that indicates how well the gains between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in gain is report- ed (typically in dB) as gain matching.

Offset Matching

Like gain matching, offset matching is a figure of merit that indicates how well the offsets between the two chan- nels are matched to each other. The same input signal is applied to both channels and the maximum deviation in offset is reported (typically in %FSR) as offset matching.

Pin Configuration

TOP VIEW		REFOUT	SHREF
	REFIN			PD	G/T	DD	DD	DD	DD	DORA	D11A	D10A	D9A	D8A	D7A	D6A	D5A
	REFIN			PD	G/T	V	V	V	OV	DORA	D11A	D10A	D9A	D8A	D7A	D6A	D5A
	68	67	66	65	64	63	62	61	60	59	58	57	56	55	54	53	52
GND	1																51	D4A
INAP	2																50	D3A
INAN	3																49	D2A
GND	4																48	D1A
GND	5																47	D0A
COMA	6																46	N.C.
REFAP	7																45	N.C.
REFAN	8																44	DAV
GND	9							MAX12527									43	OVDD
REFBN	10							MAX12527									42	DORB
REFBN	10																42	DORB
REFBP	11																41	D11B
COMB	12																40	D10B
GND	13																39	D9B
GND	14																38	D8B
INBN	15		EXPOSED PADDLE (GND)														37	D7B
INBP	16		EXPOSED PADDLE (GND)															D6B
INBP	16																36	D6B
GND	17																35	D5B
	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32	33	34
	DIFFCLK/SECLK	CLKN	CLKP	DIV2	DIV4	DD	DD	DD	DD	DD	N.C.	N.C.	D0B	D1B	D2B	D3B	D4B
						DD	DD	V	V	OV	N.C.
						V	V	THIN QFN
						V	V

MAX12527

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Image 27

Maxim MAX12527 manual Pin Configuration, Gain Matching, Offset Matching

Contents

Ordering Information FeaturesGeneral Description Applications Conversion Rate Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Analog Input INAP, INAN, INBP, Inbn Parameter Symbol Conditions MIN TYP MAX Units Interchannel Characteristics Internal Reference RefoutVcom Digital Outputs D0A-D11A, D0B-D11B, DORA, DORB, DAV Parameter Symbol Conditions MIN TYPClock Inputs CLKP, Clkn Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 DIFFCLK/SECLK = GND Power RequirementsD0A-D11A, Dora Ovdd FFT Plot 32,768-POINT Data Record Typical Operating CharacteristicsTiming Characteristics Figure FFT Plot 16,384-POINT Data Record MAX12527 THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHz FIN = 70MHz, AIN = -0.5dBFSTHD, Sfdr vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS SNR, Sinad vs. Temperature fIN = 175MHz, AIN = -0.5dBFS Pin Description PIN Name FunctionSame side of the PC board D3B D0BD1B D2B Refin Detailed DescriptionShref Refout Functional Diagram Reference Output Reference ConfigurationsReference Mode Analog Inputs and Input Track-and-Hold T/H Amplifier Clock Input and Clock Control Lines Clock Duty-Cycle Equalizer DIV4 DIV2 Function System Timing Requirements D11A-D0A D11B-D0B CODE10 Equivalent BinaryD11A-D0A DOR Vrefp Vrefn Power-Down Input Binary-to-Gray and Gray-to-Binary Code Conversion Using Transformer Coupling Single-Ended AC-Coupled Input SignalApplications Information Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCs MAX12527 Grounding, Bypassing, and Board Layout Parameter Definitions Total Harmonic Distortion THD Aperture DelayFull-Power Bandwidth Overdrive Recovery Time Pin Configuration Gain MatchingOffset Matching 68L QFN THIN.EPS Package Information