Dual, 65Msps, 12-Bit, IF/Baseband ADC
Bypass REFIN and REFOUT to GND with a 0.1µF capac- itor. The REFIN input impedance is very large (>50MΩ). When driving REFIN through a resistive divider, use resistances ≥10kΩ to avoid loading REFOUT.
Buffered external reference mode is virtually identical to the internal reference mode except that the reference source is derived from an external reference and not the MAX12527’s internal bandgap reference. In buffered external reference mode, apply a stable reference volt- age source between 0.7V to 2.3V at REFIN. Pins COM_, REF_P, and REF_N are
Connect REFIN to GND to enter unbuffered external ref- erence mode. Connecting REFIN to GND deactivates the
For all reference modes, bypass REFOUT with a 0.1µF and REFIN with a 4.7µF capacitor to GND.
The MAX12527 also features a shared reference mode, in which the user can achieve better
Connect SHREF to GND to disable the shared refer- ence mode of the MAX12527. In this independent refer- ence mode, a better
For detailed circuit suggestions and how to drive the ADC in buffered/unbuffered external reference mode, see the Applications Information section.
Clock Duty-Cycle Equalizer
The MAX12527 has an internal clock
The clock
Clock Input and Clock Control Lines
The MAX12527 accepts both differential and single- ended clock inputs with a wide 25% to 75% input clock
duty cycle. For
external
Low clock jitter is required for the specified SNR perfor- mance of the MAX12527. The analog inputs are sam- pled on the falling (rising) edge of CLKP (CLKN), requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship:
SNR = | 20 × | | 1 |
| | |
log |
|
|
| | ||
| × π × fIN × |
| ||||
|
| 2 | tJ |
where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For instance, assuming that clock jitter is the only noise source, to obtain the specified 69.8dB of SNR with an input fre- quency of 175MHz the system must have less than 0.29ps of clock jitter. However, in reality there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than 0.14ps to obtain the speci- fied 69.8dB of SNR at 175MHz.
MAX12527
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