Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN =
+85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER |
| SYMBOL |
| CONDITIONS |
| MIN | TYP | MAX |
| UNITS |
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REF_P Sink Current |
| IREFAP |
| VREF_P = 2.418V |
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| 1.2 |
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| mA |
| IREFBP |
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REF_N Source Current |
| IREFAN |
| VREF_N = 0.882V |
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| 0.85 |
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| mA |
| IREFBN |
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COM_ Sink Current |
| ICOMA |
| VCOM_ = 1.65V |
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| 0.85 |
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| mA |
| ICOMB |
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REF_P, REF_N Capacitance |
| CREF_P, |
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| 13 |
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| pF |
| CREF_N |
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COM_ Capacitance |
| CCOM_ |
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| 6 |
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| pF |
CLOCK INPUTS (CLKP, CLKN) |
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| VIH |
| DIFFCLK/SECLK = GND, CLKN = GND |
| 0.8 x |
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| V | |
Threshold |
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| VDD |
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| VIL |
| DIFFCLK/SECLK = GND, CLKN = GND |
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| 0.2 x |
| V | |
Threshold |
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| VDD |
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Minimum Differential Clock Input |
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| DIFFCLK/SECLK = OVDD |
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| 0.2 |
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Voltage Swing |
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Differential Input |
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| DIFFCLK/SECLK = OVDD |
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| VDD / 2 |
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| V |
Voltage |
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CLK_ Input Resistance |
| RCLK |
| Each input (Figure 4) |
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| 5 |
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| kΩ |
CLK_ Input Capacitance |
| CCLK |
| Each input |
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| 2 |
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| pF |
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4) |
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Input High Threshold |
| VIH |
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| 0.8 x |
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| V |
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| OVDD |
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Input Low Threshold |
| VIL |
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| 0.2 x |
| V |
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| OVDD |
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Input Leakage Current |
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| OVDD applied to input |
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| ±5 |
| µA |
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| Input connected to ground |
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| ±5 |
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Digital Input Capacitance |
| CDIN |
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| 5 |
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| pF |
DIGITAL OUTPUTS |
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| 0.2 |
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| VOL |
| ISINK = 200µA |
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| V | ||
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| DAV: ISINK = 600µA |
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| 0.2 |
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| OVDD - |
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| VOH |
| ISOURCE = 200µA |
| 0.2 |
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| V | |
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| DAV: ISOURCE = 600µA |
| OVDD - |
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| 0.2 |
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| ILEAK |
| OVDD applied to input |
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| ±5 |
| µA | |
(Note 4) |
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| Input connected to ground |
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| ±5 |
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MAX12527
_______________________________________________________________________________________ 5