Motorola manual Functional Description, MVME6100 Features Summary, Feature Description

Functional Description

4

This chapter describes the MVME6100 on a block diagram level.

Features

The following table lists the features of the MVME6100.

Table 4-1. MVME6100 Features Summary

Feature	Description
Processor	– Single 1.267 GHz MPC7457 processor
	– Bus clock frequency at 133 MHz
	– 36-bit address, 64-bit data buses
	– Integrated L1 and L2 cache
L3 Cache	– Bus clock frequency at 211 MHz (when supported by processor)
	– Up to 2MB using DDR SRAM
Flash	– Two banks (A & B) of soldered Intel StrataFlash devices
	– 8 to 64MB supported on each bank
	– Boot bank is switch selectable between banks
	– Bank A has combination of software and hardware write-protect
	scheme
	– Bank B top 1MB block can be write-protected through
	software/hardware write-protect control
System Memory	– Two banks on board for up to 1Gb using 256Mb or 512Mb devices
	– Bus clock frequency at 133 MHz
Memory Controller	– Provided by Marvell MV64360 system controller
PCI Host Bridge
Dual 10/100/1000 Ethernet
Interrupt Controller
PCI Interface
I2C Interface
NVRAM	– 32KB provided by MK48T37 with SnapHat battery backup
Real-Time Clock
Watchdog Timer
On-board Peripheral	– Dual 10/100/1000 Ethernet ports routed to front panel RJ-45
Support	connectors, one optionally routed to P2 backplane
	– Two asynchronous serial ports provided by an ST16C554D; one
	serial port is routed to a front panel RJ-45 connector and the
	second serial port is routed to an on-board header (J29, as factory
	default build configuration).
PCI/PMC	– Two 32/64-bit PMC slots with front-panel I/O plus P2 rear I/O as
	specified by IEEE P1386
	– 33/66 MHz PCI or 66/100 MHz PCI-X

MVME6100 Installation and Use (V6100A/IH2) 35