Motorola MVME6100 manual CPU Bus Interface, Memory Controller Interface

Chapter 4 Functional Description

All of the above interfaces are connected through a cross bar fabric. The cross bar enables concurrent transactions between units. For example, the cross bar can simultaneously control:

■A Gigabit Ethernet MAC fetching a descriptor from the integrated SRAM

■The CPU reading from the DRAM

■The DMA moving data from the device bus to the PCI bus

CPU Bus Interface

The CPU interface (master and slave) operates at 133 MHz and +2.5V signal levels using MPX bus modes. The CPU bus has a 36-bit address and 64-bit data buses. The MV64360 supports up to eight pipelined transactions per processor. There are 21 address windows supported in the CPU interface:

■Four for SDRAM chip selects

■Five for device chip selects

■Five for the PCI_0 interface (four memory + one I/O)

■Five for the PCI_1 interface (four memory + one I/O)

■One for the MV64360 integrated SRAM

■One for the MV64360 internal registers space

Each window is defined by base and size registers and can decode up to 4GB space (except for the integrated SRAM, which is fixed to 256KB). Refer to the MV64360 Data Sheet, listed in Appendix C, Related Documentation, for additional information and programming details.

Memory Controller Interface

The MVME6100 supports two banks of DDR SDRAM using 256Mb/ 512Mb DDR SDRAM devices on-board. 1Gb DDR non-stacked SDRAM devices may be used when available. 133 MHz operation should be used for all memory options. The SDRAM supports ECC and the MV64360 supports single-bit and double-bit error detection and single-bit error correction of all SDRAM reads and writes.

The SDRAM controller supports a wide range of SDRAM timing parameters. These parameters can be configured through the SDRAM Mode register and the SDRAM Timing Parameters register. Refer to the MV64360 Data Sheet, listed in Appendix C, Related Documentation, for additional information and programming details.

The DRAM controller contains four transaction queues—two write buffers and two read buffers. The DRAM controller does not necessarily issue DRAM transactions in the same order that it receives the transactions. The MV64360 is targeted to support full PowerPC cache coherency between CPU L1/L2 caches and DRAM.

38MVME6100 Installation and Use (V6100A/IH2)