Motorola MVME6100 manual VMEbus Interface, PMCspan Interface, Flash Memory, System Memory

Chapter 4 Functional Description

PCI Bus Arbitration

PCI arbitration is performed by the MV64360 system controller. The MV64360 integrates two PCI arbiters, one for each PCI interface (PCI bus 0/1). Each arbiter can handle up to six external agents plus one internal agent (PCI bus 0/1 master). The internal PCI arbiter REQ#/GNT# signals are multiplexed on the MV64360 MPP pins. The internal PCI arbiter is disabled by default (the MPP pins function as general-purpose inputs). Software configures the MPP pins to function as request/grant pairs for the internal PCI arbiter. The arbitration pairs for the MVME6100 are assigned to the MPP pins as shown in the MVME6100 Programmer’s Guide.

VMEbus Interface

The VMEbus interface is provided by the Tsi148 ASIC. Refer to the Tsi148 User’s Manual available from Tundra Semiconductor for additional information as listed in Appendix 1, Related Documentation. 2eSST operations are not supported on 3-row backplanes. You must use VME64x (VITA 1.5) compatible backplanes, such as 5-row backplanes, to achieve maximum VMEbus performance.

PMCspan Interface

The MVME6100 provides a PCI expansion connector to add more PMC interfaces than the two on the MVME6100 board. The PMCspan interface is provided through the PCI6520 PCIx/PCIx bridge.

Flash Memory

The MVME6100 contains two banks of flash memory accessed via the device controller bus contained within the MV64360 device. Both banks are soldered on board and have different write-protection schemes.

System Memory

MVME6100 system memory consists of double-data-rate SDRAMs. The DDR SDRAMs support two data transfers per clock cycle. The memory device is a standard monolithic (32M x 8 or 64M x 8) DDR, 8-bit wide, 66-pin, TSSOPII package. Both banks are provided on board the MVME6100 and operate at 133 MHz clock frequency with both banks populated.

Asynchronous Serial Ports

The MVME6100 board contains one EXAR ST16C554D quad UART (QUART) device connected to the MV64360 device controller bus to provide asynchronous debug ports. The QUART supports up to four asynchronous serial ports, two of which are used on the MVME6100.

42MVME6100 Installation and Use (V6100A/IH2)