Chapter 4 – SocketModem Parallel Interface – A Programmer's Description

Table 4–1. Parallel Interface Registers

Register

Register

 

 

 

BIT No.

 

 

 

No.

Name

7

6

5

4

3

2

1

0

7

Scratch Register (SCR)

 

 

 

Scratch Register

 

 

 

6

Modem Status Register

Data

Ring

Data Set

Clear to

Delta Data

Trailing

Delta Data

Delta Clear

 

(MSR)

Carrier

Indicator

Ready

Send CTS)

Carrier

Edge of Ring

Set Ready

to Send

 

 

Detect

(RI)

(DSR)

 

Detect

Indicator

(DDSR)

(DCTS)

 

 

(DCD)

 

 

 

(DDCD)

(TERI)

 

 

5

Line Status Register

RX

Transmitter

Transmitter

Break

Framing

Parity

Overrun

Receiver

 

(LSR)

FIFO

Empty

Buffer

Interrupt

Error

Error

Error

Data

 

 

Error

(TEMT)

Register

(BI)

(FE)

(PE)

(OE)

Ready

 

 

 

 

Empty

 

 

 

 

(DR)

 

 

 

 

(THRE)

 

 

 

 

 

4

Modem Control

0

0

0

Local

Out 2

Out 1

Request

Data

 

Register (MCR)

 

 

 

Loopback

 

 

to Send

Terminal

 

 

 

 

 

 

 

 

(RTS)

Ready

 

 

 

 

 

 

 

 

 

(DTR)

3

Line Control Register

Divisor

Set

Stick

Even

Parity

Number

Word

Word Length

 

(LCR)

Latch

Break

Parity

Parity

Enable

of Stop

Length

Select

 

 

Access Bit

 

 

Select

(PEN)

Bits

Select

Bit 0

 

 

(DLAB)

 

 

(EPS)

 

(STB)

Bit 1

(WLSO)

 

 

 

 

 

 

 

 

(WLS1)

 

2

Interrupt Identify

FIFOs

FIFOs

0

0

Pending

Pending

Pending

“0” if

 

Register (IIR)

Enabled

Enabled

 

 

Interrupt ID

Interrupt ID

Interrupt ID

Interrupt

 

(Read Only)

 

 

 

 

Bit 2

Bit 1

Bit 0

Pending

2

FIFO Control Register

Receiver

Receiver

Reserved

Reserved

DMA

TX FIFO

RX FIFO

FIFO

 

(FCR)

Trigger

Trigger

 

 

Mode

Reset

Reset

Enable

 

(Write Only)

MSB

LSB

 

 

Select

 

 

 

1

Interrupt Enable

0

0

0

0

Enable

Enable

Enable

Enable

(DLAB = 0)

Register (ER)

 

 

 

 

Modem

Receiver

Transmitter

Received

 

 

 

 

 

 

Status

Line Status

Holding

Data

 

 

 

 

 

 

Interrupt

Interrupt

Register

Available

 

 

 

 

 

 

(EDSSI)

(ELSI)

Empty

Interrupt

 

 

 

 

 

 

 

 

Interrupt

(ERBFI)

 

 

 

 

 

 

 

 

(ETBEI)

 

0

Transmitter Buffer

 

 

Transmitter

FIFO Buffer Register (Write Only)

 

 

(DLAB = 0)

Register

 

 

 

 

 

 

 

 

 

(THR)

 

 

 

 

 

 

 

 

0

Receiver Buffer

 

 

Receiver FIFO Buffer Register (Read Only)

 

 

(DLAB = 0)

Register (RBR)

 

 

 

 

 

 

 

 

1

Divisor Latch MSB

 

 

 

Divisor Latch MSB

 

 

 

(DLAB = 1)

Register (DLM)

 

 

 

 

 

 

 

 

0

Divisor Latch LSB

 

 

 

Divisor Latch LSB

 

 

 

(DLAB = 1)

Register (DLL)

 

 

 

 

 

 

 

 

Multi-Tech Systems, Inc. SocketModem MT5600SMI Developer’s Guide

19

Page 19
Image 19
Multi-Tech Systems MT5600SMI-L92, MT5600SMI-XL34, MT5600SMI-P92 manual Parallel Interface Registers, Register BIT No Name