Multi-Tech Systems MT5600SMI-92, MT5600SMI-XL34, MT5600SMI-P92 Parallel Host Bus Timing Table

Chapter 3 – Electrical Characteristics

Parallel Host Bus Timing

Parallel Host Bus Timing Table

Symbol

Parameter

Min

Max

Units

READ (See Notes)

tAS	Address Setup	5	-	ns
tAH	Address Hold	10	-	ns
tCS	Chip Select Setup	0	-	ns
tCH	Chip Select Hold	10	-	ns
tRD	RD Strobe Width	45	-	ns
tDD	Read Data Delay	-	25	ns
tDRH	Read Data Hold	5	-	ns
	WRITE (See	Notes)
tAS	Address Setup	5	-	ns
tAH	Address Hold	15	-	ns
tCS	Chip Select Setup	0	-	ns
tCH	Chip Select Hold	10	-	ns
tWT	WT Strobe Width	75	-	ns
tDS	Write Data Setup (see Note 4)	-	20	ns
tDWH	Write Data Hold (see Note 5)	5	-	ns

Notes:

1. When the host executes consecutive Rx FIFO reads, a minimum delay of 2 times the internal CPU clock cycle plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of RD to the falling edge of the next Host Rx FIFO RD clock.

2. When the host executes consecutive Tx FIFO writes, a minimum delay of 2 times the internal CPU clock cycle plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of WT to the falling edge of the next Host Tx FIFO WT clock.

3. tRD' tWT = tCYC + 15 ns.

4. tDS is measured from the point at which both CS and WT are active.

5. tDWH is measured from the point at which either CS and WT become active.

6. Clock Frequency = 28.224 MHz clock.

Multi-Tech Systems, Inc. SocketModem MT5600SMI Developer’s Guide 16