Chapter4 SignalConnections
6023E/6024E/6025EUser Manual 4-38 ni.com
A counter on your devicein ternally generates the STARTSCANsignal
unlessyou select some external source. This counter is started by the
TRIG1 signal and is stopped either bysoftware or by the sample counter.
Scansgenerated by either an internal or external STARTSCAN signal are
inhibitedunless they occur within a DAQ sequence.Scans occurring w ithin
aDAQ sequence can be gated by either the hardware (AIGATE) signal or
softwarecommand register gate.
CONVERT* Signal
Any PFI pin can externally input the CONVERT* signal, which is
available as an output on the PFI2/CONVERT* pin.
Refert o Figures 4-17 and 4-18 for the relationship of CONVERT*to the
DAQsequence.
As aninpu t, theC ONVERT*signal is configured in the edge-detection
mode. Youcan select any PFI pin as the source for CONVERT* and
configurethe polarity selection for either ri sing orfalling edg e. The
selectededge of the CONV ERT*signal initiates an A/D conversion.
The ADC switchesto hold mode within60 ns of the selected edge. This
hold-mode delay time is a function of temperature and does not vary from
oneconversion to the next. Separate the CONVERT* pulses by at least 5 ยตs
(200 kHz sample rate).
Asan output, the CONVERT* signal reflects the actual convert pulse that
isconnected to the ADC. This is true even if the conversions are externally
generated byanother PFI. Th eo utput is an activelow pulse with a pulse
width of 50 to 150 ns. This output is set to high impedance at startup.
Figures 4-27 and 4-28 showthe input and outp ut timing requirements for
the CONVERT*signal.
Figure4-27. CONVERT* Input Signal Timing
Rising-Edge
Polarity
Falling-Edge
Polarity
tw
tw=10 ns minimum