Chapter4 SignalConnections
©NationalInstruments Corporation 4-39 6023E/6024E/6025EUser Manual
Figure4-28. CONVERT*Output Signal Timing
The sampleinterval counter on the device normally generates the
CONVERT*signal unless you select some external source. The counter is
startedby the STARTSCANsignal and contin ues to count downand reload
itselfuntil the s can isfinished. It then reloads itself in preparation for the
nextSTARTSCAN pulse.
A/D conversionsgenerated by either an internal or external CONVERT*
signalare inhibitedunless they occur within a DAQsequence. Scans
occurring within a DAQsequence can be gated by either the hardware
(AIGATE)signal or software command register gate.
AIGATESignal
Any PFIpin can ext ernally input the AIGATE signal, which is not
available as an output on the I/O connector. The AIGATE signal can
mask offscans ina DAQ sequence. You can configure the PFI pin you
selectas thesource for the AIGATE signal in either the level-detection or
edge-detection mode. You can configure the polarity selection forthe
PFI pin for either active high or active low.
In the level-detectionmode if AIGATE is active, the STARTSCANsignal
ismasked off and no scans can occur. In the edge-detection mode, the first
activeedge disables the STARTSCAN signal, and the second activeedge
enablesSTARTSCAN.
The AIGATEsignal can neither stop a scan in progress nor continue a
previouslygated-off scan; in other words, once a scan has started, AIGATE
does not gate offconversions until the beginning of the next scan and,
conversely,if conversions are gated off, AIGATEdoes not gate them back
on until the beginning of the next scan.
t
w
t
w
=50-150 ns