Contents
6023E/6024E/6025EUser Manual viii ni.com
Figures
Figure 1-1. The Relationship Between the Programming Environment,
NI-DAQ,and YourHardware ...............................................................1-5
Figure 3-1. PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E
BlockDiagram ......................................................................................3-1
Figure3-2. DAQCard-6024E BlockDiagram .........................................................3-2
Figure3-3. Dithering ...............................................................................................3-5
Figure3-4. CONVERT* SignalRouting .................................................................3-8
Figure3-5. PCI RTSI Bus Signal Connection .........................................................3-10
Figure3-6. PXI RTSI Bus Signal Connection......................................................... 3-11
Figure4-1. I/O Connector Pin Assignment for the 6023E/6024E ...........................4-2
Figure4-2. I/O Connector Pin Assignment for the 6025E ...................................... 4-3
Figure4-3. Programmable Gain Instrumentation Amplifier ( PGIA)...................... 4-10
Figure4-4. Summary of Analog Input Connections ............................................... 4-12
Figure 4-5. Differential Input Connections for Ground-Referenced Signals.......... 4-14
Figure 4-6. Differential Input Connections for Nonreferenced Signals.................. 4-15
Figure 4-7. Single-Ended Input Connections for Nonreferenced or
FloatingSignals ....................................................................................4-18
Figure 4-8. Single-Ended Input Connections for Ground-Referenced Signals....... 4-19
Figure4-9. Analog OutputConnections ..................................................................4-20
Figure4-10. DigitalI /O Connections ........................................................................4-21
Figure4-11. DigitalI /O Connections Block Diagram...............................................4-22
Figure 4-12. DIOChannel Configured for High DIO Power-up State with
ExternalLoad ........................................................................................4-24
Figure4-13. Timing Specifications for Mode 1 Input Transfer................................ 4-27
Figure4-14. Timing Specifications for Mode 1 Output Transfer .............................4-28
Figure4 -15. TimingSpecifications for Mode 2 Bidirectional Transfer....................4-29
Figure4-16. TimingI/O Connections....................................................................... 4-31
Figure4-17. TypicalPosttriggered Acquisition........................................................ 4-32
Figure4-18. TypicalPretriggered Acquisition..........................................................4-33
Figure4-19. SCANCLKSignal Timing....................................................................4-33
Figure4-20. EXTSTROBE*Signal Timing............................................................. 4-34
Figure4-21. TRIG1I nput SignalTiming ..................................................................4-34
Figure4-22. TRIG1O utput SignalTiming ...............................................................4-35
Figure4-23. TRIG2I nput SignalTiming ..................................................................4-36
Figure4-24. TRIG2O utput SignalTiming ...............................................................4-36
Figure4-25. STARTSCANInput Signal Timing ......................................................4-37
Figure4-26. STARTSCANO utput SignalTiming ...................................................4-37
Figure4-27. CONVERT*Input Signal Timing ........................................................ 4-38
Figure4-28. CONVERT*Output Signal Timing ......................................................4-39
Figure4-29. SISOURCE Signal Timing ...................................................................4-40